sec/intel/txt/ramstage.c: Extract heap init into a function
Heap initialization is self-contained, so place it into a separate function. Also, do it after the MSEG registers have been written, so that all register writes are grouped together. This has no impact. Change-Id: Id108f4cfcd2896d881d9ba267888f7ed5dd984fa Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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@ -194,103 +194,8 @@ static void push_sinit_heap(u8 **heap_ptr, void *data, size_t data_length)
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}
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}
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/**
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* Finalize the TXT device.
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*
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* - Lock TXT register.
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* - Protect TSEG using DMA protected regions.
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* - Setup TXT regions.
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* - Place SINIT ACM in TXT_SINIT memory segment.
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* - Fill TXT BIOSDATA region.
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*/
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static void lockdown_intel_txt(void *unused)
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static void txt_initialize_heap(void)
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{
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const uint64_t status = read64((void *)TXT_SPAD);
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uintptr_t tseg_base;
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size_t tseg_size;
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smm_region(&tseg_base, &tseg_size);
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if (status & ACMSTS_TXT_DISABLED)
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return;
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printk(BIOS_INFO, "TEE-TXT: Locking TEE...\n");
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/* Lock TXT config, unlocks TXT_HEAP_BASE */
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if (intel_txt_run_bios_acm(ACMINPUT_LOCK_CONFIG) < 0) {
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printk(BIOS_ERR, "TEE-TXT: Failed to lock registers.\n");
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printk(BIOS_ERR, "TEE-TXT: SINIT won't be supported.\n");
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return;
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}
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/*
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* Document Number: 558294
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* Chapter 5.5.6.1 DMA Protection Memory Region
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*/
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const u8 dpr_capable = !!(read64((void *)TXT_CAPABILITIES) &
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TXT_CAPABILITIES_DPR);
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printk(BIOS_INFO, "TEE-TXT: DPR capable %x\n", dpr_capable);
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if (dpr_capable) {
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/* Verify the DPR settings on the MCH and mirror them to TXT public space */
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union dpr_register dpr = txt_get_chipset_dpr();
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printk(BIOS_DEBUG, "TEE-TXT: MCH DPR 0x%08x\n", dpr.raw);
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printk(BIOS_DEBUG, "TEE-TXT: MCH DPR base @ 0x%08x size %u MiB\n",
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(dpr.top - dpr.size) * MiB, dpr.size);
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// DPR TODO: implement SA_ENABLE_DPR in the intelblocks
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if (!dpr.lock) {
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printk(BIOS_ERR, "TEE-TXT: MCH DPR not locked.\n");
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return;
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}
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if (!dpr.epm || !dpr.prs) {
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printk(BIOS_ERR, "TEE-TXT: MCH DPR protection not active.\n");
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return;
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}
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if (dpr.size < CONFIG_INTEL_TXT_DPR_SIZE) {
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printk(BIOS_ERR, "TEE-TXT: MCH DPR configured size is too small.\n");
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return;
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}
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if (dpr.top * MiB != tseg_base) {
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printk(BIOS_ERR, "TEE-TXT: MCH DPR top does not equal TSEG base.\n");
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return;
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}
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/* Clear reserved bits */
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dpr.prs = 0;
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dpr.epm = 0;
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write64((void *)TXT_DPR, dpr.raw);
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printk(BIOS_INFO, "TEE-TXT: TXT.DPR 0x%08x\n",
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read32((void *)TXT_DPR));
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}
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/*
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* Document Number: 558294
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* Chapter 5.5.6.3 Intel TXT Heap Memory Region
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*/
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write64((void *)TXT_HEAP_SIZE, 0xE0000);
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write64((void *)TXT_HEAP_BASE,
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ALIGN_DOWN(tseg_base - read64((void *)TXT_HEAP_SIZE), 4096));
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/*
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* Document Number: 558294
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* Chapter 5.5.6.2 SINIT Memory Region
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*/
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write64((void *)TXT_SINIT_SIZE, 0x20000);
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write64((void *)TXT_SINIT_BASE,
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ALIGN_DOWN(read64((void *)TXT_HEAP_BASE) -
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read64((void *)TXT_SINIT_SIZE), 4096));
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/*
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* BIOS Data Format
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* Chapter C.2
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@ -392,6 +297,104 @@ static void lockdown_intel_txt(void *unused)
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/* SinitMLEData */
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/* FIXME: Does firmware need to write this? */
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push_sinit_heap(&heap_struct, NULL, 0);
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}
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/**
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* Finalize the TXT device.
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*
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* - Lock TXT register.
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* - Protect TSEG using DMA protected regions.
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* - Setup TXT regions.
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* - Place SINIT ACM in TXT_SINIT memory segment.
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* - Fill TXT BIOSDATA region.
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*/
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static void lockdown_intel_txt(void *unused)
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{
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const uint64_t status = read64((void *)TXT_SPAD);
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uintptr_t tseg_base;
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size_t tseg_size;
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smm_region(&tseg_base, &tseg_size);
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if (status & ACMSTS_TXT_DISABLED)
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return;
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printk(BIOS_INFO, "TEE-TXT: Locking TEE...\n");
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/* Lock TXT config, unlocks TXT_HEAP_BASE */
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if (intel_txt_run_bios_acm(ACMINPUT_LOCK_CONFIG) < 0) {
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printk(BIOS_ERR, "TEE-TXT: Failed to lock registers.\n");
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printk(BIOS_ERR, "TEE-TXT: SINIT won't be supported.\n");
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return;
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}
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/*
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* Document Number: 558294
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* Chapter 5.5.6.1 DMA Protection Memory Region
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*/
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const u8 dpr_capable = !!(read64((void *)TXT_CAPABILITIES) &
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TXT_CAPABILITIES_DPR);
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printk(BIOS_INFO, "TEE-TXT: DPR capable %x\n", dpr_capable);
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if (dpr_capable) {
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/* Verify the DPR settings on the MCH and mirror them to TXT public space */
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union dpr_register dpr = txt_get_chipset_dpr();
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printk(BIOS_DEBUG, "TEE-TXT: MCH DPR 0x%08x\n", dpr.raw);
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printk(BIOS_DEBUG, "TEE-TXT: MCH DPR base @ 0x%08x size %u MiB\n",
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(dpr.top - dpr.size) * MiB, dpr.size);
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// DPR TODO: implement SA_ENABLE_DPR in the intelblocks
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if (!dpr.lock) {
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printk(BIOS_ERR, "TEE-TXT: MCH DPR not locked.\n");
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return;
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}
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if (!dpr.epm || !dpr.prs) {
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printk(BIOS_ERR, "TEE-TXT: MCH DPR protection not active.\n");
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return;
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}
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if (dpr.size < CONFIG_INTEL_TXT_DPR_SIZE) {
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printk(BIOS_ERR, "TEE-TXT: MCH DPR configured size is too small.\n");
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return;
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}
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if (dpr.top * MiB != tseg_base) {
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printk(BIOS_ERR, "TEE-TXT: MCH DPR top does not equal TSEG base.\n");
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return;
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}
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/* Clear reserved bits */
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dpr.prs = 0;
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dpr.epm = 0;
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write64((void *)TXT_DPR, dpr.raw);
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printk(BIOS_INFO, "TEE-TXT: TXT.DPR 0x%08x\n",
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read32((void *)TXT_DPR));
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}
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/*
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* Document Number: 558294
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* Chapter 5.5.6.3 Intel TXT Heap Memory Region
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*/
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write64((void *)TXT_HEAP_SIZE, 0xE0000);
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write64((void *)TXT_HEAP_BASE,
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ALIGN_DOWN(tseg_base - read64((void *)TXT_HEAP_SIZE), 4096));
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/*
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* Document Number: 558294
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* Chapter 5.5.6.2 SINIT Memory Region
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*/
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write64((void *)TXT_SINIT_SIZE, 0x20000);
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write64((void *)TXT_SINIT_BASE,
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ALIGN_DOWN(read64((void *)TXT_HEAP_BASE) -
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read64((void *)TXT_SINIT_SIZE), 4096));
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/*
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* FIXME: Server-TXT capable platforms need to install an STM in SMM and set up MSEG.
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write64((void *)TXT_MSEG_SIZE, 0);
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write64((void *)TXT_MSEG_BASE, 0);
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txt_initialize_heap();
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if (CONFIG(INTEL_TXT_LOGGING))
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txt_dump_regions();
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}
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