mb/google/guybrush: Enable AP <-> H1 communication

Configure H1 I2C and Interrupt GPIOs during the early initialization.
Add devicetree configuration for H1 device and enable the required
config items.

BUG=b:180528902
TEST=Build Guybrush mainboard.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I040a5e6101bab0c7425d7b6cc6fbed3b479a5a44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

src/mainboard/google/guybrush/Kconfig

@@ -22,6 +22,8 @@ config BOARD_SPECIFIC_OPTIONS
 	select HAVE_EM100_SUPPORT
 	select HAVE_SPD_IN_CBFS
 	select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_I2C_TPM_CR50
+	select MAINBOARD_HAS_TPM2
 	select SOC_AMD_CEZANNE
 	select SOC_AMD_COMMON_BLOCK_USE_ESPI
 
@@ -50,6 +52,14 @@ config AMD_FWM_POSITION_INDEX
 	help
 	  TODO: might need to be adapted for better placement of files in cbfs
 
+config DRIVER_TPM_I2C_BUS
+	hex
+	default 0x03
+
+config DRIVER_TPM_I2C_ADDR
+	hex
+	default 0x50
+
 config EFS_SPI_READ_MODE
 	int
 	default 0 if EM100 # Normal read mode

src/mainboard/google/guybrush/variants/baseboard/devicetree.cb

@@ -132,4 +132,13 @@ chip soc/amd/cezanne
 			end
 		end
 	end # domain
+
+	device ref i2c_3 on
+		chip drivers/i2c/tpm
+			register "hid" = ""GOOG0005""
+			register "desc" = ""Cr50 TPM""
+			register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_3)"
+			device i2c 50 on end
+		end
+	end
 end	# chip soc/amd/cezanne

src/mainboard/google/guybrush/variants/baseboard/gpio.c

@@ -163,6 +163,12 @@ static const struct soc_amd_gpio base_gpio_table[] = {
 
 /* Early GPIO configuration */
 static const struct soc_amd_gpio early_gpio_table[] = {
+	/* GSC_SOC_INT_L */
+	PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
+	/* I2C3_SCL */
+	PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE),
+	/* I2C3_SDA */
+	PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE),
 	/* ESPI1_DATA0 */
 	PAD_NF(GPIO_104, SPI2_DO_ESPI2_D0, PULL_NONE),
 	/* ESPI1_DATA1 */