AMD binaryPI: Declare IOAPIC IDs

There is no longer a relation between MAX_CPUS and IOAPIC IDs,
start the cleanup with new declarations.

Change-Id: I65888550e359e55402d99e8816ece2061cfcccbc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Kyösti Mälkki 2022-12-05 19:31:01 +02:00
parent d76beb8129
commit 8f86fa0da1
5 changed files with 22 additions and 8 deletions

View File

@ -3,6 +3,7 @@
#include <acpi/acpi.h> #include <acpi/acpi.h>
#include <arch/ioapic.h> #include <arch/ioapic.h>
#include <northbridge/amd/nb_common.h> #include <northbridge/amd/nb_common.h>
#include <southbridge/amd/pi/hudson/ioapic.h>
unsigned long acpi_fill_madt(unsigned long current) unsigned long acpi_fill_madt(unsigned long current)
{ {
@ -10,11 +11,11 @@ unsigned long acpi_fill_madt(unsigned long current)
current = acpi_create_madt_lapics_with_nmis(current); current = acpi_create_madt_lapics_with_nmis(current);
/* Write SB800 IOAPIC, only one */ /* Write SB800 IOAPIC, only one */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, CONFIG_MAX_CPUS, current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, FCH_IOAPIC_ID,
IO_APIC_ADDR, 0); IO_APIC_ADDR, 0);
/* TODO: Remove the hardcode */ /* TODO: Remove the hardcode */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, CONFIG_MAX_CPUS + 1, current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, GNB_IOAPIC_ID,
IO_APIC2_ADDR, 24); IO_APIC2_ADDR, 24);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)

View File

@ -23,6 +23,7 @@
#include <northbridge/amd/nb_common.h> #include <northbridge/amd/nb_common.h>
#include <northbridge/amd/agesa/agesa_helper.h> #include <northbridge/amd/agesa/agesa_helper.h>
#include <southbridge/amd/pi/hudson/pci_devs.h> #include <southbridge/amd/pi/hudson/pci_devs.h>
#include <southbridge/amd/pi/hudson/ioapic.h>
#include <amdblocks/cpu.h> #include <amdblocks/cpu.h>
#define MAX_NODE_NUMS MAX_NODES #define MAX_NODE_NUMS MAX_NODES
@ -221,7 +222,7 @@ static void nb_set_resources(struct device *dev)
static void northbridge_init(struct device *dev) static void northbridge_init(struct device *dev)
{ {
setup_ioapic((u8 *)IO_APIC2_ADDR, CONFIG_MAX_CPUS + 1); setup_ioapic((u8 *)IO_APIC2_ADDR, GNB_IOAPIC_ID);
} }
static unsigned long acpi_fill_hest(acpi_hest_t *hest) static unsigned long acpi_fill_hest(acpi_hest_t *hest)
@ -253,7 +254,7 @@ unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current)
ivhd_ioapic->dte_setting = IVHD_DTE_LINT_1_PASS | IVHD_DTE_LINT_0_PASS | ivhd_ioapic->dte_setting = IVHD_DTE_LINT_1_PASS | IVHD_DTE_LINT_0_PASS |
IVHD_DTE_SYS_MGT_NO_TRANS | IVHD_DTE_NMI_PASS | IVHD_DTE_SYS_MGT_NO_TRANS | IVHD_DTE_NMI_PASS |
IVHD_DTE_EXT_INT_PASS | IVHD_DTE_INIT_PASS; IVHD_DTE_EXT_INT_PASS | IVHD_DTE_INIT_PASS;
ivhd_ioapic->handle = CONFIG_MAX_CPUS; /* FCH IOAPIC ID */ ivhd_ioapic->handle = FCH_IOAPIC_ID;
ivhd_ioapic->source_dev_id = PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC); ivhd_ioapic->source_dev_id = PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC);
ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC; ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC;
current += sizeof(ivrs_ivhd_special_t); current += sizeof(ivrs_ivhd_special_t);
@ -263,7 +264,7 @@ unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current)
ivhd_ioapic->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; ivhd_ioapic->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV;
ivhd_ioapic->reserved = 0x0000; ivhd_ioapic->reserved = 0x0000;
ivhd_ioapic->dte_setting = 0x00; ivhd_ioapic->dte_setting = 0x00;
ivhd_ioapic->handle = CONFIG_MAX_CPUS + 1; /* GNB IOAPIC ID */ ivhd_ioapic->handle = GNB_IOAPIC_ID;
ivhd_ioapic->source_dev_id = PCI_DEVFN(0, 1); ivhd_ioapic->source_dev_id = PCI_DEVFN(0, 1);
ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC; ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC;
current += sizeof(ivrs_ivhd_special_t); current += sizeof(ivrs_ivhd_special_t);

View File

@ -9,6 +9,7 @@
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h> #include <northbridge/amd/agesa/agesa_helper.h>
#include <northbridge/amd/nb_common.h> #include <northbridge/amd/nb_common.h>
#include <southbridge/amd/pi/hudson/ioapic.h>
void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
{ {
@ -64,8 +65,8 @@ void platform_BeforeInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late)
* when IOMMU build config is enabled otherwise AGESA will skip * when IOMMU build config is enabled otherwise AGESA will skip
* it during IOMMU init and IVRS generation. * it during IOMMU init and IVRS generation.
*/ */
Late->GnbLateConfiguration.GnbIoapicId = CONFIG_MAX_CPUS + 1; Late->GnbLateConfiguration.GnbIoapicId = GNB_IOAPIC_ID;
Late->GnbLateConfiguration.FchIoapicId = CONFIG_MAX_CPUS; Late->GnbLateConfiguration.FchIoapicId = FCH_IOAPIC_ID;
} }
/* Code for creating CDIT requires hop count table. If it is not /* Code for creating CDIT requires hop count table. If it is not

View File

@ -0,0 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef AMD_BLOCK_IOAPIC_H
#define AMD_BLOCK_IOAPIC_H
/* Since the old APIC bus isn't used any more, the IOAPIC IDs could be < CONFIG_MAX_CPUS */
#define FCH_IOAPIC_ID (CONFIG_MAX_CPUS)
#define GNB_IOAPIC_ID (CONFIG_MAX_CPUS + 1)
#endif /* AMD_BLOCK_IOAPIC_H */

View File

@ -5,6 +5,7 @@
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <device/smbus.h> #include <device/smbus.h>
#include <arch/ioapic.h> #include <arch/ioapic.h>
#include <southbridge/amd/pi/hudson/ioapic.h>
#include "hudson.h" #include "hudson.h"
#include "smbus.c" #include "smbus.c"
@ -21,7 +22,7 @@
static void sm_init(struct device *dev) static void sm_init(struct device *dev)
{ {
setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS); setup_ioapic(VIO_APIC_VADDR, FCH_IOAPIC_ID);
} }
static int lsmbus_recv_byte(struct device *dev) static int lsmbus_recv_byte(struct device *dev)