GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/asus/p5gc-mx: Use common/gpio.h 

Should have been included in 62902ca45d "sb/ich7: Use common/gpio.h to
set up GPIOs", which was not rebased on addition of this board.

Change-Id: If4547ee43ce6a7a6e4af67e9364613e48f989401
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18047
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Arthur Heymans 2017-01-06 20:01:57 +01:00 committed by Martin Roth
parent b5623dede7
commit 8f8d56dded
3 changed files with 131 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/asus/p5gc-mx/Makefile.inc
View File

@ -1 +1,3 @@
ramstage-y += cstates.c ramstage-y += cstates.c
romstage-y += gpio.c

129
src/mainboard/asus/p5gc-mx/gpio.c Normal file
View File

@ -0,0 +1,129 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Arthur Heymans <arthur@aheymans.xyz>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <southbridge/intel/common/gpio.h>
const struct pch_gpio_set1 pch_gpio_set1_mode = {
.gpio0 = GPIO_MODE_GPIO,
.gpio6 = GPIO_MODE_GPIO,
.gpio7 = GPIO_MODE_GPIO,
.gpio8 = GPIO_MODE_GPIO,
.gpio9 = GPIO_MODE_GPIO,
.gpio10 = GPIO_MODE_GPIO,
.gpio11 = GPIO_MODE_GPIO,
.gpio12 = GPIO_MODE_GPIO,
.gpio13 = GPIO_MODE_GPIO,
.gpio14 = GPIO_MODE_GPIO,
.gpio15 = GPIO_MODE_GPIO,
.gpio16 = GPIO_MODE_GPIO,
.gpio18 = GPIO_MODE_GPIO,
.gpio19 = GPIO_MODE_GPIO,
.gpio20 = GPIO_MODE_GPIO,
.gpio21 = GPIO_MODE_GPIO,
.gpio24 = GPIO_MODE_GPIO,
.gpio25 = GPIO_MODE_GPIO,
.gpio26 = GPIO_MODE_GPIO,
.gpio27 = GPIO_MODE_GPIO,
.gpio28 = GPIO_MODE_GPIO,
};
const struct pch_gpio_set1 pch_gpio_set1_direction = {
.gpio0 = GPIO_DIR_OUTPUT,
.gpio6 = GPIO_DIR_INPUT,
.gpio7 = GPIO_DIR_INPUT,
.gpio8 = GPIO_DIR_INPUT,
.gpio9 = GPIO_DIR_INPUT,
.gpio10 = GPIO_DIR_INPUT,
.gpio11 = GPIO_DIR_OUTPUT,
.gpio12 = GPIO_DIR_INPUT,
.gpio13 = GPIO_DIR_INPUT,
.gpio14 = GPIO_DIR_INPUT,
.gpio15 = GPIO_DIR_INPUT,
.gpio16 = GPIO_DIR_OUTPUT,
.gpio18 = GPIO_DIR_OUTPUT,
.gpio19 = GPIO_DIR_INPUT,
.gpio20 = GPIO_DIR_OUTPUT,
.gpio21 = GPIO_DIR_INPUT,
.gpio24 = GPIO_DIR_OUTPUT,
.gpio25 = GPIO_DIR_OUTPUT,
.gpio26 = GPIO_DIR_OUTPUT,
.gpio27 = GPIO_DIR_OUTPUT,
.gpio28 = GPIO_DIR_OUTPUT,
};
const struct pch_gpio_set1 pch_gpio_set1_level = {
.gpio0 = GPIO_LEVEL_LOW,
.gpio11 = GPIO_LEVEL_HIGH,
.gpio16 = GPIO_LEVEL_LOW,
.gpio18 = GPIO_LEVEL_HIGH,
.gpio20 = GPIO_LEVEL_HIGH,
.gpio24 = GPIO_LEVEL_LOW,
.gpio25 = GPIO_LEVEL_HIGH,
.gpio26 = GPIO_LEVEL_LOW,
.gpio27 = GPIO_LEVEL_LOW,
.gpio28 = GPIO_LEVEL_LOW,
};
const struct pch_gpio_set1 pch_gpio_set1_blink = {
};
const struct pch_gpio_set1 pch_gpio_set1_invert = {
.gpio13 = GPIO_INVERT,
.gpio14 = GPIO_INVERT,
};
const struct pch_gpio_set2 pch_gpio_set2_mode = {
.gpio32 = GPIO_MODE_NATIVE,
.gpio33 = GPIO_MODE_NATIVE,
.gpio34 = GPIO_MODE_NATIVE,
.gpio35 = GPIO_MODE_NATIVE,
.gpio36 = GPIO_MODE_NATIVE,
.gpio37 = GPIO_MODE_NATIVE,
.gpio38 = GPIO_MODE_NATIVE,
.gpio39 = GPIO_MODE_NATIVE,
};
const struct pch_gpio_set2 pch_gpio_set2_direction = {
.gpio32 = GPIO_DIR_OUTPUT,
.gpio33 = GPIO_DIR_OUTPUT,
.gpio34 = GPIO_DIR_OUTPUT,
.gpio35 = GPIO_DIR_OUTPUT,
.gpio36 = GPIO_DIR_INPUT,
.gpio37 = GPIO_DIR_INPUT,
.gpio38 = GPIO_DIR_INPUT,
.gpio39 = GPIO_DIR_INPUT,
};
const struct pch_gpio_set2 pch_gpio_set2_level = {
.gpio32 = GPIO_LEVEL_HIGH,
.gpio33 = GPIO_LEVEL_HIGH,
.gpio34 = GPIO_LEVEL_LOW,
.gpio35 = GPIO_LEVEL_LOW,
};
const struct pch_gpio_map mainboard_gpio_map = {
.set1 = {
.mode = &pch_gpio_set1_mode,
.direction = &pch_gpio_set1_direction,
.level = &pch_gpio_set1_level,
.blink = &pch_gpio_set1_blink,
.invert = &pch_gpio_set1_invert,
},
.set2 = {
.mode = &pch_gpio_set2_mode,
.direction = &pch_gpio_set2_direction,
.level = &pch_gpio_set2_level,
},
};

17
src/mainboard/asus/p5gc-mx/romstage.c
View File

@ -44,23 +44,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
#define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V) #define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V)
void setup_ich7_gpios(void)
{
/* TODO: This is highly board specific and should be moved */
printk(BIOS_DEBUG, " GPIOS...");
/* General Registers */
outl(0x1f3dffc1, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
outl(0xe0e8f7c2, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
outl(0xe2febb7e, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
/* Output Control Registers */
outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */
/* Input Control Registers */
outl(0x00006000, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
outl(0x000000ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */
outl(0x000000f0, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */
outl(0x00030033, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */
}
/* /*
* BSEL0 is connected with GPIO32 * BSEL0 is connected with GPIO32
* BSEL1 is connected with GPIO33 with inversed logic * BSEL1 is connected with GPIO33 with inversed logic