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mainboard/amd: Incorrect usage of logical vs. bitwise and 

Spotted by Clang

Change-Id: I26201c7f5e421c38d3965d8e7e62c4a8e670e449
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5833
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
This commit is contained in:
Edward O'Callaghan 2014-05-24 04:01:38 +10:00 committed by Idwer Vollering
parent 6cec824a28
commit 8f9132fab1
2 changed files with 2 additions and 2 deletions
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2
src/mainboard/amd/dinar/gpio.c
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@ -256,7 +256,7 @@ gpioEarlyInit(
// WAIT POWER READY: GPIO28 (MXM_PWRGD) // WAIT POWER READY: GPIO28 (MXM_PWRGD)
//while (!(Mmio8 (GpioMmioAddr, SB_GPIO_REG28) && BIT7)){} //while (!(Mmio8 (GpioMmioAddr, SB_GPIO_REG28) && BIT7)){}
ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8); ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8);
while (!(Data8 && BIT7)) while (!(Data8 & BIT7))
{ {
ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8); ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8);
} }

2
src/mainboard/amd/torpedo/gpio.c
View File

@ -255,7 +255,7 @@ gpioEarlyInit(
// WAIT POWER READY: GPIO28 (MXM_PWRGD) // WAIT POWER READY: GPIO28 (MXM_PWRGD)
//while (!(Mmio8 (GpioMmioAddr, SB_GPIO_REG28) && BIT7)){} //while (!(Mmio8 (GpioMmioAddr, SB_GPIO_REG28) && BIT7)){}
ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8); ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8);
while (!(Data8 && BIT7)) while (!(Data8 & BIT7))
{ {
ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8); ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8);
} }