ARMv7/Exynos: Fix memory location assumptions
This patch cleans out a lot of unused variables in the ARM Kconfig files and introduces CONFIG_RAMSTAGE_BASE which is similar to CONFIG_RAMBASE on x86. This gets rid of the hard coded assumption that on ARM coreboot is always executed at the lowest DRAM address. But in fact, this might not be true because we might want coreboot to live at the end of RAM, or in SRAM Change-Id: I03e992645f9eb730e39a521aa21f702959311f74 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://chromium-review.googlesource.com/168645 Reviewed-by: David Hendrix <dhendrix@chromium.org> Tested-by: David Hendrix <dhendrix@chromium.org> (cherry picked from commit 15b87892eb2d5e27759c49dc6c8c7e626f651d77) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6634 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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@ -1,7 +1,7 @@
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/*
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/*
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* Memory map:
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* Memory map:
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*
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*
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* CONFIG_RAMBASE : text segment
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* CONFIG_RAMSTAGE_BASE : text segment
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* : rodata segment
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* : rodata segment
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* : data segment
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* : data segment
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* : bss segment
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* : bss segment
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@ -31,7 +31,7 @@ PHDRS
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SECTIONS
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SECTIONS
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{
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{
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. = CONFIG_SYS_SDRAM_BASE;
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. = CONFIG_RAMSTAGE_BASE;
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/* First we place the code and read only data (typically const declared).
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/* First we place the code and read only data (typically const declared).
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* This could theoretically be placed in rom.
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* This could theoretically be placed in rom.
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*/
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*/
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@ -111,9 +111,6 @@ SECTIONS
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}
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}
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_eheap = .;
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_eheap = .;
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_stack = CONFIG_STACK_BOTTOM;
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_estack = CONFIG_STACK_TOP;
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/* The ram segment. This includes all memory used by the memory
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/* The ram segment. This includes all memory used by the memory
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* resident copy of coreboot, except the tables that are produced on
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* resident copy of coreboot, except the tables that are produced on
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* the fly, but including stack and heap.
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* the fly, but including stack and heap.
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@ -121,6 +118,12 @@ SECTIONS
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_ram_seg = _text;
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_ram_seg = _text;
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_eram_seg = _eheap;
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_eram_seg = _eheap;
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/* The stack lives in SRAM in a different location, so keep
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* it out of ram_seg
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*/
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_stack = CONFIG_STACK_BOTTOM;
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_estack = CONFIG_STACK_TOP;
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/* Discard the sections we don't need/want */
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/* Discard the sections we don't need/want */
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/DISCARD/ : {
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/DISCARD/ : {
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/*
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/*
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* Memory map:
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* Memory map:
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*
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*
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* CONFIG_RAMBASE : text segment
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* CONFIG_ROMSTAGE_BASE : text segment
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* : rodata segment
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* : rodata segment
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* : data segment
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* : data segment
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* : bss segment
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* : bss segment
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@ -38,6 +38,9 @@ config CBFS_ROM_OFFSET
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hex "offset of CBFS data in ROM"
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hex "offset of CBFS data in ROM"
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default 0x0A000
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default 0x0A000
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config SYS_SDRAM_BASE
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hex
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default 0x40000000
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# Example SRAM/iRAM map for Exynos5250 platform:
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# Example SRAM/iRAM map for Exynos5250 platform:
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#
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#
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@ -54,9 +57,9 @@ config ROMSTAGE_BASE
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hex
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hex
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default 0x02030000
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default 0x02030000
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config ROMSTAGE_SIZE
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config RAMSTAGE_BASE
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hex
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hex
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default 0x10000
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default SYS_SDRAM_BASE
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# Stack may reside in either IRAM or DRAM. We will define it to live
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# Stack may reside in either IRAM or DRAM. We will define it to live
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# at the top of IRAM for now.
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# at the top of IRAM for now.
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@ -90,12 +93,4 @@ config TTB_BUFFER
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hex "memory address of the TTB buffer"
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hex "memory address of the TTB buffer"
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default 0x02058000
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default 0x02058000
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config TTB_SIZE
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hex "size of the TTB buffer"
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default 0x4000
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config SYS_SDRAM_BASE
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hex
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default 0x40000000
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endif
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endif
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hex "offset of CBFS data in ROM"
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hex "offset of CBFS data in ROM"
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default 0x0A000
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default 0x0A000
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config SYS_SDRAM_BASE
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hex
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default 0x20000000
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# Example SRAM/iRAM map for Exynos5420 platform:
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# Example SRAM/iRAM map for Exynos5420 platform:
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#
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#
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@ -63,9 +66,9 @@ config ROMSTAGE_BASE
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hex
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hex
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default 0x02030000
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default 0x02030000
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config ROMSTAGE_SIZE
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config RAMSTAGE_BASE
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hex
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hex
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default 0x20000
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default SYS_SDRAM_BASE
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# Stack may reside in either IRAM or DRAM. We will define it to live
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# Stack may reside in either IRAM or DRAM. We will define it to live
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# at the top of IRAM for now.
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# at the top of IRAM for now.
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@ -90,11 +93,6 @@ config STACK_BOTTOM
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hex
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hex
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default 0x0206f000
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default 0x0206f000
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# The romstage stack must be large enough to contain the lzma buffer
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config ROMSTAGE_STACK_SIZE
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hex
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default 0x4000
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# STACK_SIZE is for the ramstage core and thread stacks.
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# STACK_SIZE is for the ramstage core and thread stacks.
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# It must be a power of 2, to make the cpu_info computation work,
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# It must be a power of 2, to make the cpu_info computation work,
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# and cpu_info needs to work to make SMP startup and threads work.
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# and cpu_info needs to work to make SMP startup and threads work.
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@ -116,12 +114,4 @@ config TTB_BUFFER
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hex "memory address of the TTB buffer"
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hex "memory address of the TTB buffer"
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default 0x02058000
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default 0x02058000
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config TTB_SIZE
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hex "size of the TTB buffer"
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default 0x4000
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config SYS_SDRAM_BASE
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hex
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default 0x20000000
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endif
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endif
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@ -33,7 +33,7 @@ config MAINBOARD_DIR
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config MAINBOARD_PART_NUMBER
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config MAINBOARD_PART_NUMBER
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string
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string
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default "QEMU ARMV7"
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default "QEMU ARMv7"
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config MAX_CPUS
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config MAX_CPUS
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int
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int
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string
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string
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default "ARM Ltd."
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default "ARM Ltd."
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config SYS_SDRAM_BASE
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hex "SDRAM base address"
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default 0x01000000
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config DRAM_SIZE_MB
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config DRAM_SIZE_MB
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int
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int
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default 1024
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default 1024
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@ -62,17 +66,13 @@ config BOOTBLOCK_BASE
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hex
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hex
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default 0x00010000
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default 0x00010000
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config ID_SECTION_BASE
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hex
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default 0x0001f000
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config ROMSTAGE_BASE
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config ROMSTAGE_BASE
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hex
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hex
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default 0x00020000
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default 0x00020000
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config ROMSTAGE_SIZE
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config RAMSTAGE_BASE
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hex
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hex
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default 0x20000
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default SYS_SDRAM_BASE
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config BOOTBLOCK_ROM_OFFSET
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config BOOTBLOCK_ROM_OFFSET
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hex
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hex
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hex
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hex
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default 0x0003ff00
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default 0x0003ff00
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config SYS_SDRAM_BASE
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hex "SDRAM base address"
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default 0x01000000
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endif # BOARD_EMULATION_QEMU_ARMV7
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endif # BOARD_EMULATION_QEMU_ARMV7
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