libpayload: Remove bitfield use from EHCI data structures
We agreed that bitfields are a Bad Idea[tm]. Change-Id: If4c4cb748af340e2721b89fea8e035da0632971f Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/480 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Peter Stuge <peter@stuge.se>
This commit is contained in:
Patrick Georgi
Peter Stuge
parent
b0b4a52b70
commit
8fa2787a0d
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@ -34,19 +34,19 @@
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static void dump_td(u32 addr)
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{
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qtd_t *td = phys_to_virt(addr);
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debug("td at phys(%x): active: %x, halted: %x, data_buf_err: %x\n babble: %x, xact_err: %x, missed_mframe: %x\n splitxstate: %x, perr: %x\n\n",
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addr, td->active, td->halted, td->data_buf_err, td->babble, td->xact_err, td->missed_mframe, td->splitxstate, td->perr);
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debug("- cerr: %x, total_len: %x\n\n", td->cerr, td->total_len);
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debug("td at phys(%x): status: %x\n\n", addr, td->token & QTD_STATUS_MASK);
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debug("- cerr: %x, total_len: %x\n\n", (td->token & QTD_CERR_MASK) >> QTD_CERR_SHIFT,
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(td->token & QTD_TOTAL_LEN_MASK) >> QTD_TOTAL_LEN_SHIFT);
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}
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static void ehci_start (hci_t *controller)
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{
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EHCI_INST(controller)->operation->rs = 1;
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EHCI_INST(controller)->operation->usbcmd |= HC_OP_RS;
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}
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static void ehci_stop (hci_t *controller)
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{
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EHCI_INST(controller)->operation->rs = 0;
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EHCI_INST(controller)->operation->usbcmd &= ~HC_OP_RS;
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}
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static void ehci_reset (hci_t *controller)
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@ -61,20 +61,19 @@ static void ehci_shutdown (hci_t *controller)
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enum { EHCI_OUT=0, EHCI_IN=1, EHCI_SETUP=2 };
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/* returns handled bytes */
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int fill_td(qtd_t *td, void* data, int datalen)
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/* returns handled bytes. assumes that the fields it writes are empty on entry */
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static int fill_td(qtd_t *td, void* data, int datalen)
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{
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u32 total_len = 0;
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u32 page_minus_1 = 0;
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u32 page_no = 0;
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u32 start = virt_to_phys(data);
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u32 page = start & ~4095;
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u32 offset = start & 4095;
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u32 page_len = 4096 - offset;
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td->c_page = 0;
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td->bufptr0 = page;
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td->cur_off = offset;
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td->token |= 0 << QTD_CPAGE_SHIFT;
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td->bufptrs[page_no++] = start;
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if (datalen <= page_len) {
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total_len = datalen;
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@ -82,26 +81,25 @@ int fill_td(qtd_t *td, void* data, int datalen)
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datalen -= page_len;
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total_len += page_len;
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do {
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while (page_no < 5) {
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/* we have a continguous mapping between virtual and physical memory */
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page += 4096;
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td->bufptrs[page_minus_1] = page;
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td->bufptrs[page_no++] = page;
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if (datalen <= 4096) {
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total_len += datalen;
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break;
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}
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page_minus_1++;
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datalen -= 4096;
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total_len += 4096;
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} while (page_minus_1<4);
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}
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}
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td->total_len = total_len;
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td->token |= total_len << QTD_TOTAL_LEN_SHIFT;
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return total_len;
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}
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/* free up data structures */
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void free_qh_and_tds(ehci_qh_t *qh, qtd_t *cur)
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static void free_qh_and_tds(ehci_qh_t *qh, qtd_t *cur)
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{
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qtd_t *next;
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while (cur) {
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@ -112,14 +110,14 @@ void free_qh_and_tds(ehci_qh_t *qh, qtd_t *cur)
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free(qh);
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}
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int wait_for_tds(qtd_t *head)
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static int wait_for_tds(qtd_t *head)
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{
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int result = 0;
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qtd_t *cur = head;
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while (1) {
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if (0) dump_td(virt_to_phys(cur));
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while (cur->active && !cur->halted) udelay(60);
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if (cur->halted) {
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while ((cur->token & QTD_ACTIVE) && !(cur->token & QTD_HALTED)) udelay(60);
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if (cur->token & QTD_HALTED) {
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printf("ERROR with packet\n");
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dump_td(virt_to_phys(cur));
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debug("-----------------\n");
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@ -146,17 +144,16 @@ static int ehci_bulk (endpoint_t *ep, int size, u8 *data, int finalize)
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qtd_t *cur = head;
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while (1) {
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memset(cur, 0, sizeof(qtd_t));
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cur->active = 1;
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cur->pid = pid;
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cur->cerr = 0;
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cur->token = QTD_ACTIVE |
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(pid << QTD_PID_SHIFT) |
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(0 << QTD_CERR_SHIFT);
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u32 chunk = fill_td(cur, data, size);
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size -= chunk;
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data += chunk;
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cur->alt_terminate = 1;
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cur->alt_next_qtd = QTD_TERMINATE;
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if (size == 0) {
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cur->next_qtd = virt_to_phys(0);
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cur->terminate = 1;
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cur->next_qtd = virt_to_phys(0) | QTD_TERMINATE;
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break;
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} else {
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qtd_t *next = memalign(32, sizeof(qtd_t));
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@ -168,36 +165,35 @@ static int ehci_bulk (endpoint_t *ep, int size, u8 *data, int finalize)
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/* create QH */
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ehci_qh_t *qh = memalign(32, sizeof(ehci_qh_t));
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memset(qh, 0, sizeof(ehci_qh_t));
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qh->horiz_link_ptr = virt_to_phys(qh);
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qh->type = 1; // FIXME: proper symbols for type. this is QH
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qh->addr = ep->dev->address;
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qh->ep = endp;
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qh->eps = ep->dev->speed;
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qh->dtc = 0;
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qh->reclaim_head = 1;
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qh->max_packet_len = ep->maxpacketsize;
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qh->nak_cnt_reload = 0;
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qh->pipe_multiplier = 3;
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qh->horiz_link_ptr = virt_to_phys(qh) | QH_QH;
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qh->epchar = ep->dev->address |
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(endp << QH_EP_SHIFT) |
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(ep->dev->speed << QH_EPS_SHIFT) |
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(0 << QH_DTC_SHIFT) |
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(1 << QH_RECLAIM_HEAD_SHIFT) |
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(ep->maxpacketsize << QH_MPS_SHIFT) |
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(0 << QH_NAK_CNT_SHIFT);
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qh->epcaps = 3 << QH_PIPE_MULTIPLIER_SHIFT;
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qh->td.next_qtd = virt_to_phys(head);
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qh->td.dt = ep->toggle;
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head->dt = ep->toggle;
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qh->td.token |= (ep->toggle?QTD_TOGGLE_DATA1:0);
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head->token |= (ep->toggle?QTD_TOGGLE_DATA1:0);
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/* hook up QH */
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EHCI_INST(ep->dev->controller)->operation->asynclistaddr = virt_to_phys(qh);
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/* start async schedule */
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EHCI_INST(ep->dev->controller)->operation->async_sched_enable = 1;
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while (!EHCI_INST(ep->dev->controller)->operation->async_sched_status) ; /* wait */
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EHCI_INST(ep->dev->controller)->operation->usbcmd |= HC_OP_ASYNC_SCHED_EN;
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while (!(EHCI_INST(ep->dev->controller)->operation->usbsts & HC_OP_ASYNC_SCHED_STAT)) ; /* wait */
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/* wait for result */
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result = wait_for_tds(head);
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/* disable async schedule */
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EHCI_INST(ep->dev->controller)->operation->async_sched_enable = 0;
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while (EHCI_INST(ep->dev->controller)->operation->async_sched_status) ; /* wait */
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EHCI_INST(ep->dev->controller)->operation->usbcmd &= ~HC_OP_ASYNC_SCHED_EN;
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while (EHCI_INST(ep->dev->controller)->operation->usbsts & HC_OP_ASYNC_SCHED_STAT) ; /* wait */
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ep->toggle = cur->dt;
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ep->toggle = (cur->token & QTD_TOGGLE_MASK) >> QTD_TOGGLE_SHIFT;
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free_qh_and_tds(qh, head);
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return result;
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@ -217,16 +213,16 @@ static int ehci_control (usbdev_t *dev, direction_t dir, int drlen, void *devreq
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qtd_t *head = memalign(32, sizeof(qtd_t));
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qtd_t *cur = head;
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memset(cur, 0, sizeof(qtd_t));
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cur->active = 1;
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cur->dt = toggle;
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cur->pid = EHCI_SETUP;
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cur->cerr = 3;
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cur->token = QTD_ACTIVE |
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(toggle?QTD_TOGGLE_DATA1:0) |
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(EHCI_SETUP << QTD_PID_SHIFT) |
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(3 << QTD_CERR_SHIFT);
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if (fill_td(cur, devreq, drlen) != drlen) {
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printf("ERROR: couldn't send the entire device request\n");
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}
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qtd_t *next = memalign(32, sizeof(qtd_t));
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cur->next_qtd = virt_to_phys(next);
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cur->alt_terminate = 1;
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cur->alt_next_qtd = QTD_TERMINATE;
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/* FIXME: We're limited to 16-20K (depending on alignment) for payload for now.
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* Figure out, how toggle can be set sensibly in this scenario */
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@ -234,58 +230,56 @@ static int ehci_control (usbdev_t *dev, direction_t dir, int drlen, void *devreq
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toggle ^= 1;
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cur = next;
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memset(cur, 0, sizeof(qtd_t));
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cur->active = 1;
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cur->dt = toggle;
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cur->pid = (dir == OUT)?EHCI_OUT:EHCI_IN;
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cur->cerr = 3;
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cur->token = QTD_ACTIVE |
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(toggle?QTD_TOGGLE_DATA1:0) |
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(((dir == OUT)?EHCI_OUT:EHCI_IN) << QTD_PID_SHIFT) |
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(3 << QTD_CERR_SHIFT);
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if (fill_td(cur, data, dalen) != dalen) {
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printf("ERROR: couldn't send the entire control payload\n");
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}
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next = memalign(32, sizeof(qtd_t));
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cur->next_qtd = virt_to_phys(next);
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cur->alt_terminate = 1;
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cur->alt_next_qtd = QTD_TERMINATE;
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}
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toggle = 1;
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cur = next;
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memset(cur, 0, sizeof(qtd_t));
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cur->active = 1;
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cur->dt = toggle;
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cur->pid = (dir == OUT)?EHCI_IN:EHCI_OUT;
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cur->cerr = 0;
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cur->token = QTD_ACTIVE |
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(toggle?QTD_TOGGLE_DATA1:QTD_TOGGLE_DATA0) |
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((dir == OUT)?EHCI_IN:EHCI_OUT) << QTD_PID_SHIFT |
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(0 << QTD_CERR_SHIFT);
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fill_td(cur, NULL, 0);
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cur->next_qtd = virt_to_phys(0);
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cur->terminate = 1;
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cur->alt_terminate = 1;
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cur->next_qtd = virt_to_phys(0) | QTD_TERMINATE;
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cur->alt_next_qtd = QTD_TERMINATE;
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/* create QH */
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ehci_qh_t *qh = memalign(32, sizeof(ehci_qh_t));
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memset(qh, 0, sizeof(ehci_qh_t));
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qh->horiz_link_ptr = virt_to_phys(qh);
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qh->type = 1; // FIXME: proper symbols for type. this is QH
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qh->addr = dev->address;
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qh->ep = endp;
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qh->eps = dev->speed;
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qh->dtc = 1; /* Take data toggle from TD, as control transfers are special */
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qh->reclaim_head = 1;
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qh->max_packet_len = mlen;
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qh->non_hs_control_ep = 0; // no support for non-HS devices at this time
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qh->nak_cnt_reload = 0;
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qh->pipe_multiplier = 3;
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qh->horiz_link_ptr = virt_to_phys(qh) | QH_QH;
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qh->epchar = dev->address |
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(endp << QH_EP_SHIFT) |
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(dev->speed << QH_EPS_SHIFT) |
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(1 << QH_DTC_SHIFT) | /* ctrl transfers are special: take toggle bit from TD */
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(1 << QH_RECLAIM_HEAD_SHIFT) |
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(mlen << QH_MPS_SHIFT) |
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(0 << QH_NON_HS_CTRL_EP_SHIFT) | /* no non-HS device support yet */
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(0 << QH_NAK_CNT_SHIFT);
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qh->epcaps = 3 << QH_PIPE_MULTIPLIER_SHIFT;
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qh->td.next_qtd = virt_to_phys(head);
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/* hook up QH */
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EHCI_INST(dev->controller)->operation->asynclistaddr = virt_to_phys(qh);
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/* start async schedule */
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EHCI_INST(dev->controller)->operation->async_sched_enable = 1;
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while (!EHCI_INST(dev->controller)->operation->async_sched_status) ; /* wait */
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EHCI_INST(dev->controller)->operation->usbcmd |= HC_OP_ASYNC_SCHED_EN;
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while (!(EHCI_INST(dev->controller)->operation->usbsts & HC_OP_ASYNC_SCHED_STAT)) ; /* wait */
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result = wait_for_tds(head);
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/* disable async schedule */
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EHCI_INST(dev->controller)->operation->async_sched_enable = 0;
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while (EHCI_INST(dev->controller)->operation->async_sched_status) ; /* wait */
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EHCI_INST(dev->controller)->operation->usbcmd &= ~HC_OP_ASYNC_SCHED_EN;
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while (EHCI_INST(dev->controller)->operation->usbsts & HC_OP_ASYNC_SCHED_STAT) ; /* wait */
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free_qh_and_tds(qh, head);
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return result;
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@ -37,134 +37,35 @@
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#define FLADJ 0x61
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#define FLADJ_framelength(x) (((x)-59488)/16)
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typedef volatile union {
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u32 val;
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volatile struct {
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unsigned long current_conn_status:1;
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unsigned long conn_status_change:1;
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unsigned long port_enable:1;
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unsigned long port_enable_change:1;
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unsigned long overcurrent:1;
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unsigned long overcurrent_change:1;
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unsigned long force_port_resume:1;
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unsigned long suspend:1;
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unsigned long port_reset:1;
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unsigned long:1;
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unsigned long line_status:2;
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unsigned long pp:1;
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unsigned long port_owner:1;
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unsigned long port_indicator_control:2;
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unsigned long port_test_control:4;
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unsigned long wake_on_connect_en:1;
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unsigned long wake_on_disconnect_en:1;
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unsigned long wake_on_overcurrent_en:1;
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unsigned long:9;
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} __attribute__ ((packed));
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} __attribute__ ((packed)) portsc_t;
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typedef volatile u32 portsc_t;
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#define P_CURR_CONN_STATUS (1 << 0)
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#define P_CONN_STATUS_CHANGE (1 << 1)
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#define P_PORT_ENABLE (1 << 2)
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#define P_PORT_RESET (1 << 8)
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#define P_LINE_STATUS (3 << 10)
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#define P_LINE_STATUS_LOWSPEED (1 << 10)
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#define P_PP (1 << 12)
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#define P_PORT_OWNER (1 << 13)
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typedef volatile struct {
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#define HCS_NPORTS_MASK 0xf
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u8 caplength;
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u8 res1;
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u16 hciversion;
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union {
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u32 hcsparams;
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struct {
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unsigned long n_ports:4;
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unsigned long ppc:1;
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unsigned long:2;
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unsigned long port_routing_rules:1;
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unsigned long n_pcc:4;
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unsigned long n_cc:4;
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unsigned long p_indicator:1;
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unsigned long:3;
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unsigned long debug_port_number:4;
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unsigned long:8;
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} __attribute__ ((packed));
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};
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union {
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u32 hccparams;
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struct {
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unsigned long cap_64b_addr:1;
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unsigned long cap_prog_framelist_size:1;
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unsigned long cap_async_park:1;
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unsigned long:1;
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unsigned long isoc_sched_threshold:4;
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unsigned long eecp:8;
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unsigned long:16;
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} __attribute__ ((packed));
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};
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union {
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u64 hcsp_portroute;
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struct {
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unsigned long portroute0:4;
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unsigned long portroute1:4;
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unsigned long portroute2:4;
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unsigned long portroute3:4;
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unsigned long portroute4:4;
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unsigned long portroute5:4;
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unsigned long portroute6:4;
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unsigned long portroute7:4;
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unsigned long portroute8:4;
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unsigned long portroute9:4;
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unsigned long portroute10:4;
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unsigned long portroute11:4;
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unsigned long portroute12:4;
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unsigned long portroute13:4;
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unsigned long portroute14:4;
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unsigned long portroute15:4;
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unsigned long:4;
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} __attribute__ ((packed));
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};
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u32 hcsparams;
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u32 hccparams;
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u64 hcsp_portroute;
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} __attribute__ ((packed)) hc_cap_t;
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typedef volatile struct {
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union {
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u32 usbcmd;
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volatile struct {
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unsigned long rs:1;
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unsigned long hcreset:1;
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unsigned long frame_list_size:2;
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unsigned long periodic_sched_enable:1;
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unsigned long async_sched_enable:1;
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unsigned long irq_on_async_advance_doorbell:1;
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unsigned long light_hc_reset:1;
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unsigned long async_sched_park_mode_count:2;
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unsigned long:1;
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unsigned long async_sched_park_mode_enable:1;
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unsigned long:4;
|
||||
unsigned long irq_threshold_count:8;
|
||||
unsigned long:8;
|
||||
} __attribute__ ((packed));
|
||||
};
|
||||
union {
|
||||
u32 usbsts;
|
||||
struct {
|
||||
unsigned long usbint:1;
|
||||
unsigned long usberrint:1;
|
||||
unsigned long port_change_detect:1;
|
||||
unsigned long frame_list_rollover:1;
|
||||
unsigned long host_system_error:1;
|
||||
unsigned long irq_on_async_advance:1;
|
||||
unsigned long:6;
|
||||
unsigned long hchalted:1;
|
||||
unsigned long reclamation:1;
|
||||
unsigned long periodic_sched_status:1;
|
||||
unsigned long async_sched_status:1;
|
||||
unsigned long:16;
|
||||
} __attribute__ ((packed));
|
||||
};
|
||||
union {
|
||||
u32 usbintr;
|
||||
struct {
|
||||
unsigned long en_usb_irq:1;
|
||||
unsigned long en_usb_err_irq:1;
|
||||
unsigned long en_port_change_irq:1;
|
||||
unsigned long en_frame_list_rollover_irq:1;
|
||||
unsigned long en_host_system_error_irq:1;
|
||||
unsigned long en_irq_on_async_advance:1;
|
||||
unsigned long:26;
|
||||
} __attribute__ ((packed));
|
||||
};
|
||||
u32 usbcmd;
|
||||
#define HC_OP_RS 1
|
||||
#define HC_OP_ASYNC_SCHED_EN_SHIFT 5
|
||||
#define HC_OP_ASYNC_SCHED_EN (1 << HC_OP_ASYNC_SCHED_EN_SHIFT)
|
||||
u32 usbsts;
|
||||
#define HC_OP_ASYNC_SCHED_STAT_SHIFT 15
|
||||
#define HC_OP_ASYNC_SCHED_STAT (1 << HC_OP_ASYNC_SCHED_STAT_SHIFT)
|
||||
u32 usbintr;
|
||||
u32 frindex;
|
||||
u32 ctrldssegment;
|
||||
u32 periodiclistbase;
|
||||
|
|
@ -175,82 +76,46 @@ typedef volatile struct {
|
|||
} hc_op_t;
|
||||
|
||||
typedef volatile struct {
|
||||
union {
|
||||
u32 next_qtd;
|
||||
struct {
|
||||
unsigned long terminate:1;
|
||||
unsigned long:4;
|
||||
unsigned long:27;
|
||||
} __attribute__ ((packed));
|
||||
};
|
||||
union {
|
||||
u32 alt_next_qtd;
|
||||
struct {
|
||||
unsigned long alt_terminate:1;
|
||||
unsigned long:4;
|
||||
unsigned long:27;
|
||||
} __attribute__ ((packed));
|
||||
};
|
||||
struct {
|
||||
union {
|
||||
volatile u8 status;
|
||||
struct {
|
||||
volatile unsigned long perr:1;
|
||||
volatile unsigned long splitxstate:1;
|
||||
volatile unsigned long missed_mframe:1;
|
||||
volatile unsigned long xact_err:1;
|
||||
volatile unsigned long babble:1;
|
||||
volatile unsigned long data_buf_err:1;
|
||||
volatile unsigned long halted:1;
|
||||
volatile unsigned long active:1;
|
||||
} __attribute__ ((packed));
|
||||
};
|
||||
unsigned long pid:2;
|
||||
volatile unsigned long cerr:2;
|
||||
volatile unsigned long c_page:3;
|
||||
unsigned long ioc:1;
|
||||
volatile unsigned long total_len:15;
|
||||
volatile unsigned long dt:1;
|
||||
} __attribute__ ((packed));
|
||||
union {
|
||||
u32 bufptr0;
|
||||
struct {
|
||||
volatile unsigned long cur_off:12;
|
||||
unsigned long:20;
|
||||
} __attribute__ ((packed));
|
||||
};
|
||||
u32 bufptrs[4];
|
||||
#define QTD_TERMINATE 1
|
||||
u32 next_qtd;
|
||||
u32 alt_next_qtd;
|
||||
u32 token;
|
||||
#define QTD_STATUS_MASK 0xff
|
||||
#define QTD_HALTED (1 << 14)
|
||||
#define QTD_ACTIVE (1 << 15)
|
||||
#define QTD_PID_SHIFT 8
|
||||
#define QTD_PID_MASK (3 << QTD_PID_SHIFT)
|
||||
#define QTD_CERR_SHIFT 10
|
||||
#define QTD_CERR_MASK (3 << QTD_CERR_SHIFT)
|
||||
#define QTD_CPAGE_SHIFT 12
|
||||
#define QTD_CPAGE_MASK (7 << QTD_CPAGE_SHIFT)
|
||||
#define QTD_TOTAL_LEN_SHIFT 16
|
||||
#define QTD_TOTAL_LEN_MASK (((1<<15)-1) << QTD_TOTAL_LEN_SHIFT)
|
||||
#define QTD_TOGGLE_SHIFT 31
|
||||
#define QTD_TOGGLE_MASK (1 << 31)
|
||||
#define QTD_TOGGLE_DATA0 0
|
||||
#define QTD_TOGGLE_DATA1 (1 << QTD_TOGGLE_SHIFT)
|
||||
u32 bufptrs[5];
|
||||
u32 bufptrs64[5];
|
||||
} __attribute__ ((packed)) qtd_t;
|
||||
|
||||
typedef volatile struct {
|
||||
union {
|
||||
u32 horiz_link_ptr;
|
||||
struct {
|
||||
unsigned long terminate:1;
|
||||
unsigned long type:2;
|
||||
unsigned long:1;
|
||||
unsigned long:28;
|
||||
} __attribute__ ((packed));
|
||||
};
|
||||
struct {
|
||||
unsigned long addr:7;
|
||||
unsigned long inactivate:1;
|
||||
unsigned long ep:4;
|
||||
unsigned long eps:2;
|
||||
unsigned long dtc:1;
|
||||
unsigned long reclaim_head:1;
|
||||
unsigned long max_packet_len:11;
|
||||
unsigned long non_hs_control_ep:1;
|
||||
unsigned long nak_cnt_reload:4;
|
||||
} __attribute__ ((packed));
|
||||
struct {
|
||||
unsigned long irq_sched_mask:8;
|
||||
unsigned long split_compl_mask:8;
|
||||
unsigned long hub_addr:7;
|
||||
unsigned long port_num:7;
|
||||
unsigned long pipe_multiplier:2;
|
||||
} __attribute__ ((packed));
|
||||
u32 horiz_link_ptr;
|
||||
#define QH_TERMINATE 1
|
||||
#define QH_iTD (0<<1)
|
||||
#define QH_QH (1<<1)
|
||||
#define QH_siTD (2<<1)
|
||||
#define QH_FSTN (3<<1)
|
||||
u32 epchar;
|
||||
#define QH_EP_SHIFT 8
|
||||
#define QH_EPS_SHIFT 12
|
||||
#define QH_DTC_SHIFT 14
|
||||
#define QH_RECLAIM_HEAD_SHIFT 15
|
||||
#define QH_MPS_SHIFT 16
|
||||
#define QH_NON_HS_CTRL_EP_SHIFT 27
|
||||
#define QH_NAK_CNT_SHIFT 28
|
||||
u32 epcaps;
|
||||
#define QH_PIPE_MULTIPLIER_SHIFT 30
|
||||
volatile u32 current_td_ptr;
|
||||
volatile qtd_t td;
|
||||
} ehci_qh_t;
|
||||
|
|
|
|||
|
|
@ -54,19 +54,14 @@ static void
|
|||
ehci_rh_hand_over_port (usbdev_t *dev, int port)
|
||||
{
|
||||
volatile portsc_t *p = &(RH_INST(dev)->ports[port]);
|
||||
volatile portsc_t tmp;
|
||||
|
||||
debug("giving up port %x, it's USB1\n", port+1);
|
||||
|
||||
/* Lowspeed device. Hand over to companion */
|
||||
tmp = *p;
|
||||
tmp.port_owner = 1;
|
||||
*p = tmp;
|
||||
do {} while (!p->conn_status_change);
|
||||
*p |= P_PORT_OWNER;
|
||||
do {} while (!(*p & P_CONN_STATUS_CHANGE));
|
||||
/* RW/C register, so clear it by writing 1 */
|
||||
tmp = *p;
|
||||
tmp.conn_status_change = 1;
|
||||
*p = tmp;
|
||||
*p |= P_CONN_STATUS_CHANGE;
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -74,16 +69,15 @@ static void
|
|||
ehci_rh_scanport (usbdev_t *dev, int port)
|
||||
{
|
||||
volatile portsc_t *p = &(RH_INST(dev)->ports[port]);
|
||||
volatile portsc_t tmp;
|
||||
if (RH_INST(dev)->devices[port]!=-1) {
|
||||
debug("Unregister device at port %x\n", port+1);
|
||||
usb_detach_device(dev->controller, RH_INST(dev)->devices[port]);
|
||||
RH_INST(dev)->devices[port]=-1;
|
||||
}
|
||||
/* device connected, handle */
|
||||
if (p->current_conn_status) {
|
||||
if (*p & P_CURR_CONN_STATUS) {
|
||||
mdelay(100);
|
||||
if (p->line_status == 0x1) {
|
||||
if ((*p & P_LINE_STATUS) == P_LINE_STATUS_LOWSPEED) {
|
||||
ehci_rh_hand_over_port(dev, port);
|
||||
return;
|
||||
}
|
||||
|
|
@ -91,21 +85,17 @@ ehci_rh_scanport (usbdev_t *dev, int port)
|
|||
/* Deassert enable, assert reset. These must change
|
||||
* atomically.
|
||||
*/
|
||||
tmp = *p;
|
||||
tmp.port_enable = 0;
|
||||
tmp.port_reset = 1;
|
||||
*p = tmp;
|
||||
*p = (*p & ~P_PORT_ENABLE) | P_PORT_RESET;
|
||||
|
||||
/* Wait a bit while reset is active. */
|
||||
mdelay(50);
|
||||
|
||||
/* Deassert reset. */
|
||||
tmp.port_reset = 0;
|
||||
*p = tmp;
|
||||
*p &= ~P_PORT_RESET;
|
||||
|
||||
/* Wait for flag change to finish. The controller might take a while */
|
||||
while (p->port_reset) ;
|
||||
if (!p->port_enable) {
|
||||
while (*p & P_PORT_RESET) ;
|
||||
if (!(*p & P_PORT_ENABLE)) {
|
||||
ehci_rh_hand_over_port(dev, port);
|
||||
return;
|
||||
}
|
||||
|
|
@ -113,9 +103,7 @@ ehci_rh_scanport (usbdev_t *dev, int port)
|
|||
RH_INST(dev)->devices[port] = usb_attach_device(dev->controller, dev->address, port, 2);
|
||||
}
|
||||
/* RW/C register, so clear it by writing 1 */
|
||||
tmp = *p;
|
||||
tmp.conn_status_change = 1;
|
||||
*p = tmp;
|
||||
*p |= P_CONN_STATUS_CHANGE;
|
||||
}
|
||||
|
||||
static int
|
||||
|
|
@ -123,7 +111,7 @@ ehci_rh_report_port_changes (usbdev_t *dev)
|
|||
{
|
||||
int i;
|
||||
for (i=0; i<RH_INST(dev)->n_ports; i++) {
|
||||
if (RH_INST(dev)->ports[i].conn_status_change)
|
||||
if (RH_INST(dev)->ports[i] & P_CONN_STATUS_CHANGE)
|
||||
return i;
|
||||
}
|
||||
return -1;
|
||||
|
|
@ -143,14 +131,13 @@ ehci_rh_init (usbdev_t *dev)
|
|||
{
|
||||
int i;
|
||||
volatile portsc_t *p;
|
||||
volatile portsc_t tmp;
|
||||
|
||||
dev->destroy = ehci_rh_destroy;
|
||||
dev->poll = ehci_rh_poll;
|
||||
|
||||
dev->data = malloc(sizeof(rh_inst_t));
|
||||
|
||||
RH_INST(dev)->n_ports = EHCI_INST(dev->controller)->capabilities->n_ports;
|
||||
RH_INST(dev)->n_ports = EHCI_INST(dev->controller)->capabilities->hcsparams & HCS_NPORTS_MASK;
|
||||
RH_INST(dev)->ports = EHCI_INST(dev->controller)->operation->portsc;
|
||||
|
||||
debug("root hub has %x ports\n", RH_INST(dev)->n_ports);
|
||||
|
|
@ -159,9 +146,7 @@ ehci_rh_init (usbdev_t *dev)
|
|||
for (i=0; i < RH_INST(dev)->n_ports; i++) {
|
||||
p = &(RH_INST(dev)->ports[i]);
|
||||
RH_INST(dev)->devices[i] = -1;
|
||||
tmp = *p;
|
||||
tmp.pp = 1;
|
||||
*p = tmp;
|
||||
*p |= P_PP;
|
||||
}
|
||||
|
||||
dev->address = 0;
|
||||
|
|
|
|||
Loading…
Reference in New Issue