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amd/mct/ddr3: Correctly program maximum read latency 

The existing code inadvertently calculated the maximum read
latency for nonexistent channel 2 instead of for channels
0 and 1 as intended.  Fix the calls to the maximum read latency
training function.

Found-by: Coverity Scan #1347354
Change-Id: If34b204ac73cd20859102cc3b2f40bc99c2ce471
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/18072
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
This commit is contained in:
Timothy Pearson 2017-01-09 14:19:37 -06:00
parent bc44178f02
commit 8fa624784e
1 changed files with 3 additions and 2 deletions
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5
src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
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@ -1484,8 +1484,9 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat,
}
}
/* Calculate and program MaxRdLatency */
Calc_SetMaxRdLatency_D_Fam15(pMCTstat, pDCTstat, Channel, 0);
/* Calculate and program MaxRdLatency for both channels */
Calc_SetMaxRdLatency_D_Fam15(pMCTstat, pDCTstat, 0, 0);
Calc_SetMaxRdLatency_D_Fam15(pMCTstat, pDCTstat, 1, 0);
if (_DisableDramECC) {
mct_EnableDimmEccEn_D(pMCTstat, pDCTstat, _DisableDramECC);