arch/mips: provide proper cache primitives
This provides the opportunity to remove the kludge of disabling caches altogether in the bootblock. [pg: originally, this commit also provided automatic cache management after loading stages, ie. flush dcache, so code ends up in icache. This is done differently in upstream, so it's left out here] BUG=chrome-os-partner:34127, chrome-os-partner:31438 TEST=with this fix romstage, ramstage and payload are executed properly BRANCH=none Change-Id: I568c68d02b2cd9c1c2c9c1495ba3343c82509ccc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 95ab0f159cabf21fc100f371d451211e7d113761 Original-Change-Id: Iaf90b052073dd355ab9114e8dba9f5ef76188c94 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/232410 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9618 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Ionela Voinescu
Patrick Georgi
parent
49efaf260f
commit
8fa8f4bdc3
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@ -37,6 +37,7 @@ ifeq ($(CONFIG_ARCH_BOOTBLOCK_MIPS),y)
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bootblock-y += boot.c
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bootblock-y += bootblock.S
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bootblock-y += bootblock_simple.c
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bootblock-y += cache.c
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bootblock-y += stages.c
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bootblock-y += ../../lib/memcpy.c
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bootblock-y += ../../lib/memmove.c
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@ -62,6 +63,7 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_MIPS),y)
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romstage-y += boot.c
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romstage-$(CONFIG_EARLY_CONSOLE) += early_console.c
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romstage-y += cache.c
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romstage-y += stages.c
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romstage-y += ../../lib/memcpy.c
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romstage-y += ../../lib/memmove.c
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@ -81,6 +83,7 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_MIPS),y)
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ramstage-y += ashldi3.c
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ramstage-y += boot.c
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ramstage-y += cache.c
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ramstage-y += stages.c
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ramstage-y += tables.c
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ramstage-y += ../../lib/memcpy.c
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@ -36,16 +36,6 @@ _start:
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bne $t0, $t1, 1b
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addi $t0, $t0, 4
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/*
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* Disable caches for now, proper cache management is coming soon.
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* http://crosbug.com/p/34127
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*/
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mfc0 $t0, $16
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li $t1, -8
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and $t0, $t0, $t1
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ori $t0, $t0, 2
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mtc0 $t0, $16
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/* Run main */
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b main
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@ -0,0 +1,112 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Imagination Technologies
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/cache.h>
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#include <symbols.h>
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/* Cache operations */
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/*
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* __get_line_size:
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* Read config register
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* Isolate instruction cache line size
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* Interpret value as per MIPS manual: 2 << value
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* Return cache line size
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*/
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#define __get_line_size(cfg_no, cfg_sel, lshift, nobits) \
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({ int __res; \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set noreorder\n\t" \
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".set mips32\n\t" \
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"mfc0 $t5, "#cfg_no"," #cfg_sel"\n\t" \
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".set mips0\n\t" \
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"ext $t6, $t5," #lshift"," #nobits"\n\t" \
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"li $t7, 2\n\t" \
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"sllv %0, $t7, $t6\n\t" \
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".set pop\n\t" \
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: "=r" (__res)); \
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__res; \
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})
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/* clear_L2tag: clear L23Tag register */
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#define clear_L2tag() \
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({ \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set noreorder\n\t" \
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".set mips32\n\t" \
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"mtc0 $zero, $28, 4\n\t" \
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".set mips0\n\t" \
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".set pop\n\t" \
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); \
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})
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/* cache_op: issues cache operation for specified address */
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#define cache_op(op, addr) \
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({ \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set noreorder\n\t" \
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".set mips32\n\t" \
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"cache %0, %1\n\t" \
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".set mips0\n\t" \
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".set pop\n\t" \
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: \
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: "i" (op), "R" (*(unsigned char *)(addr))); \
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})
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void perform_cache_operation(uintptr_t start, size_t size, uint8_t operation)
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{
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u32 line_size, line_mask;
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uintptr_t end;
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line_size = get_icache_line();
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line_mask = ~(line_size-1);
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end = (start + (line_size - 1) + size) & line_mask;
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start &= line_mask;
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if ((operation & L2CACHE) == L2CACHE)
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clear_L2tag();
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while (start < end) {
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switch (operation) {
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case CACHE_CODE(ICACHE, WB_INVD):
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cache_op(CACHE_CODE(ICACHE, WB_INVD), start);
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break;
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case CACHE_CODE(DCACHE, WB_INVD):
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cache_op(CACHE_CODE(DCACHE, WB_INVD), start);
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break;
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case CACHE_CODE(L2CACHE, WB_INVD):
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cache_op(CACHE_CODE(L2CACHE, WB_INVD), start);
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break;
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default:
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return;
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}
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start += line_size;
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}
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asm("sync");
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}
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void cache_invalidate_all(uintptr_t start, size_t size)
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{
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perform_cache_operation(start, size, CACHE_CODE(ICACHE, WB_INVD));
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perform_cache_operation(start, size, CACHE_CODE(DCACHE, WB_INVD));
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perform_cache_operation(start, size, CACHE_CODE(L2CACHE, WB_INVD));
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}
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@ -20,4 +20,33 @@
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#ifndef __MIPS_ARCH_CACHE_H
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#define __MIPS_ARCH_CACHE_H
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#include <stddef.h>
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#include <stdint.h>
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#define get_icache_line() __get_line_size($16, 1, 19, 3)
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#define get_dcache_line() __get_line_size($16, 1, 10, 3)
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#define get_L2cache_line() __get_line_size($16, 2, 20, 4)
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#define CACHE_TYPE_SHIFT (0)
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#define CACHE_OP_SHIFT (2)
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#define CACHE_TYPE_MASK (0x3)
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#define CACHE_OP_MASK (0x7)
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/* Cache type */
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#define ICACHE 0x00
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#define DCACHE 0x01
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#define L2CACHE 0x03
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/* Cache operation*/
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#define WB_INVD 0x05
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#define CACHE_CODE(type, op) ((((type) & (CACHE_TYPE_MASK)) << \
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(CACHE_TYPE_SHIFT)) | \
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(((op) & (CACHE_OP_MASK)) << (CACHE_OP_SHIFT)))
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/* Perform cache operation on cache lines for target addresses */
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void perform_cache_operation(uintptr_t start, size_t size, uint8_t operation);
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/* Invalidate all caches: instruction, data, L2 data */
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void cache_invalidate_all(uintptr_t start, size_t size);
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#endif /* __MIPS_ARCH_CACHE_H */
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@ -28,8 +28,5 @@ void stage_entry(void)
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void stage_exit(void *addr)
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{
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void (*doit)(void) = addr;
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/* TODO: synci */
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doit();
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}
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