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riscv-spike: support for Spike emulation of riscv 

Spike support: QEMU RISCV is broken, and the maintainers at Berkeley
are working on it, but at the moment spike is the only way to  test
on riscv. Add support for spike console output for debugging.

Privileged ISA: Update to privileged ISA in RISCV (machine,
supervisor, hypervisor, user modes) broke exisitng RISCV asm, and
bootblock.S was updated to match the new spec. Clean old assembly

[pg: things build with gcc 4.9 now, but don't expect them to work.
Hardcoding register names into the assembler language may not be the smartest
idea of the RISCV folks.]

Change-Id: Ie2c109d3c26712c207512f74f28ce1a925e6e181
Signed-off-by: Thaminda Edirisooriya <thaminda@google.com>
Reviewed-on: http://review.coreboot.org/11078
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Thaminda Edirisooriya 2015-07-29 17:43:20 -07:00 committed by Patrick Georgi
parent d7eb0cbf9a
commit 8fad21db54
16 changed files with 1326 additions and 642 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

33
src/arch/riscv/bootblock.S
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@ -22,30 +22,33 @@
.section ".text._start", "ax", %progbits
// Maybe there's a better way.
.space 0x2000
.space 0x200
.globl _start
_start:
// pending figuring out this f-ing toolchain. Hardcode what we know works.
la sp, 0x4ef0 // .stacktop
// la a0, trap_entry
// la sp, 0x4ef0 // .stacktop
// la sp, 0x40000 // from src/mainboard/emulation/qemu-riscv
la sp, 0x7FF00 // stack start + stack size
// make room for HLS
addi sp, sp, -64 // MENTRY_FRAME_SIZE
//poison the stack
la t1, 0x40000
li t0, 0xdeadbeef
sd t0, 0(t1)
// la gp, _gp
// csrw evec, a0
# clear any pending interrupts
#if __GNUC__ < 5
csrwi clear_ipi, 0
#else
csrwi sip, 0
#endif
li a0, SR_S | SR_PS | SR_EI | SR_S64 | SR_U64
or a1, a0, SR_EF | SR_EA
csrw status, a1
csrr a1, status
csrw status, a0
// and a2, a1, SR_EF
// sw a2, have_fp, t0
// and a2, a1, SR_EA
// sw a2, have_accelerator, t0
call main
.=0x4000
.stack:

75
src/arch/riscv/include/arch/atomic.h
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@ -1,75 +0,0 @@
// See LICENSE for license details.
#ifndef _RISCV_ATOMIC_H
#define _RISCV_ATOMIC_H
#include <arch/encoding.h>
typedef struct { volatile long val; } atomic_t;
typedef struct { atomic_t lock; } spinlock_t;
#define SPINLOCK_INIT {{0}}
#define mb() __sync_synchronize()
static inline void atomic_set(atomic_t* a, long val)
{
a->val = val;
}
static inline long atomic_read(atomic_t* a)
{
return a->val;
}
static inline long atomic_add(atomic_t* a, long inc)
{
long ret = atomic_read(a);
atomic_set(a, ret + inc);
return ret;
}
static inline long atomic_swap(atomic_t* a, long val)
{
long ret = atomic_read(a);
atomic_set(a, val);
return ret;
}
static inline long atomic_cas(atomic_t* a, long compare, long swap)
{
long ret = atomic_read(a);
if (ret == compare)
atomic_set(a, swap);
return ret;
}
static inline void spinlock_lock(spinlock_t* lock)
{
do
{
while (atomic_read(&lock->lock))
;
} while (atomic_swap(&lock->lock, -1));
mb();
}
static inline void spinlock_unlock(spinlock_t* lock)
{
mb();
atomic_set(&lock->lock,0);
}
static inline long spinlock_lock_irqsave(spinlock_t* lock)
{
long flags = clear_csr(status, SR_EI);
spinlock_lock(lock);
return flags;
}
static inline void spinlock_unlock_irqrestore(spinlock_t* lock, long flags)
{
spinlock_unlock(lock);
set_csr(status, flags & SR_EI);
}
#endif

1337
src/arch/riscv/include/arch/encoding.h
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File diff suppressed because it is too large Load Diff

73
src/arch/riscv/include/atomic.h Normal file
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@ -0,0 +1,73 @@
// See LICENSE for license details.
#ifndef _RISCV_ATOMIC_H
#define _RISCV_ATOMIC_H
//#include "config.h"
#include <arch/encoding.h>
#define disable_irqsave() clear_csr(sstatus, SSTATUS_IE)
#define enable_irqrestore(flags) set_csr(sstatus, (flags) & SSTATUS_IE)
typedef struct { int lock; } spinlock_t;
#define SPINLOCK_INIT {0}
#define mb() __sync_synchronize()
#define atomic_set(ptr, val) (*(volatile typeof(*(ptr)) *)(ptr) = val)
#define atomic_read(ptr) (*(volatile typeof(*(ptr)) *)(ptr))
#ifdef PK_ENABLE_ATOMICS
# define atomic_add(ptr, inc) __sync_fetch_and_add(ptr, inc)
# define atomic_swap(ptr, swp) __sync_lock_test_and_set(ptr, swp)
# define atomic_cas(ptr, cmp, swp) __sync_val_compare_and_swap(ptr, cmp, swp)
#else
# define atomic_add(ptr, inc) ({ \
long flags = disable_irqsave(); \
typeof(ptr) res = *(volatile typeof(ptr))(ptr); \
*(volatile typeof(ptr))(ptr) = res + (inc); \
enable_irqrestore(flags); \
res; })
# define atomic_swap(ptr, swp) ({ \
long flags = disable_irqsave(); \
typeof(*ptr) res = *(volatile typeof(ptr))(ptr); \
*(volatile typeof(ptr))(ptr) = (swp); \
enable_irqrestore(flags); \
res; })
# define atomic_cas(ptr, cmp, swp) ({ \
long flags = disable_irqsave(); \
typeof(ptr) res = *(volatile typeof(ptr))(ptr); \
if (res == (cmp)) *(volatile typeof(ptr))(ptr) = (swp); \
enable_irqrestore(flags); \
res; })
#endif
static inline void spinlock_lock(spinlock_t* lock)
{
do
{
while (atomic_read(&lock->lock))
;
} while (atomic_swap(&lock->lock, -1));
mb();
}
static inline void spinlock_unlock(spinlock_t* lock)
{
mb();
atomic_set(&lock->lock,0);
}
static inline long spinlock_lock_irqsave(spinlock_t* lock)
{
long flags = disable_irqsave();
spinlock_lock(lock);
return flags;
}
static inline void spinlock_unlock_irqrestore(spinlock_t* lock, long flags)
{
spinlock_unlock(lock);
enable_irqrestore(flags);
}
#endif

73
src/arch/riscv/include/spike_util.h Normal file
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@ -0,0 +1,73 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 The ChromiumOS Authors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
#ifndef _SPIKE_UTIL_H
#define _SPIKE_UTIL_H
#include <stdint.h>
//#include <string.h>
//#include <errno.h>
#include <arch/encoding.h>
#include <atomic.h>
#define LOG_REGBYTES 3
#define REGBYTES (1 << LOG_REGBYTES)
#define STORE sd
#define HLS_SIZE 64
#define MENTRY_FRAME_SIZE HLS_SIZE
#define TOHOST_CMD(dev, cmd, payload) \
(((uint64_t)(dev) << 56) | ((uint64_t)(cmd) << 48) | (uint64_t)(payload))
#define FROMHOST_DEV(fromhost_value) ((uint64_t)(fromhost_value) >> 56)
#define FROMHOST_CMD(fromhost_value) ((uint64_t)(fromhost_value) << 8 >> 56)
#define FROMHOST_DATA(fromhost_value) ((uint64_t)(fromhost_value) << 16 >> 16)
typedef struct {
unsigned long dev;
unsigned long cmd;
unsigned long data;
unsigned long sbi_private_data;
} sbi_device_message;
typedef struct {
sbi_device_message* device_request_queue_head;
unsigned long device_request_queue_size;
sbi_device_message* device_response_queue_head;
sbi_device_message* device_response_queue_tail;
int hart_id;
int ipi_pending;
} hls_t;
#define MACHINE_STACK_TOP() ({ \
register uintptr_t sp asm ("sp"); \
(void*)((sp + RISCV_PGSIZE) & -RISCV_PGSIZE); })
// hart-local storage, at top of stack
#define HLS() ((hls_t*)(MACHINE_STACK_TOP() - HLS_SIZE))
#define MACHINE_STACK_SIZE RISCV_PGSIZE
uintptr_t htif_interrupt(uintptr_t mcause, uintptr_t* regs);
uintptr_t mcall_console_putchar(uint8_t ch);
void testPrint(void);
#endif

61
src/mainboard/emulation/spike-riscv/Kconfig Normal file
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@ -0,0 +1,61 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2014 Google Inc.
##
## This software is licensed under the terms of the GNU General Public
## License version 2, as published by the Free Software Foundation, and
## may be copied, distributed, and modified under those terms.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
# To execute, do:
# qemu-system-arm -M vexpress-a9 -m 1024M -nographic -kernel build/coreboot.rom
if BOARD_EMULATION_SPIKE_UCB_RISCV
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select SOC_UCB_RISCV
select BOARD_ROMSIZE_KB_4096
select ARCH_BOOTBLOCK_RISCV
select HAVE_UART_SPECIAL
config MAINBOARD_DIR
string
default emulation/spike-riscv
config MAINBOARD_PART_NUMBER
string
default "SPIKE RISCV"
config MAX_CPUS
int
default 1
config MAINBOARD_VENDOR
string
default "UCB"
config DRAM_SIZE_MB
int
default 32768
# Memory map for qemu riscv
#
# 0x0000_0000: jump instruction (by qemu)
# 0x0002_0000: bootblock (entry of kernel / firmware)
# 0x0003_0000: romstage, assume up to 128KB in size.
# 0x0007_ff00: stack pointer
# 0x0010_0000: CBFS header
# 0x0011_0000: CBFS data
# 0x0100_0000: reserved for ramstage
config RAMTOP
hex
default 0x1000000
endif # BOARD_EMULATION_SPIKE_UCB_RISCV

2
src/mainboard/emulation/spike-riscv/Kconfig.name Normal file
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@ -0,0 +1,2 @@
config BOARD_EMULATION_SPIKE_UCB_RISCV
bool "SPIKE ucb riscv"

26
src/mainboard/emulation/spike-riscv/Makefile.inc Normal file
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@ -0,0 +1,26 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2013 Google Inc.
##
## This software is licensed under the terms of the GNU General Public
## License version 2, as published by the Free Software Foundation, and
## may be copied, distributed, and modified under those terms.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
bootblock-y += bootblock.c
bootblock-y += uart.c
bootblock-y += spike_util.c
romstage-y += romstage.c
romstage-y += uart.c
romstage-y += spike_util.c
ramstage-y += uart.c
ramstage-y += spike_util.c
bootblock-y += memlayout.ld
romstage-y += memlayout.ld
ramstage-y += memlayout.ld

2
src/mainboard/emulation/spike-riscv/board_info.txt Normal file
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@ -0,0 +1,2 @@
Board name: QEMU RISCV
Category: emulation

34
src/mainboard/emulation/spike-riscv/bootblock.c Normal file
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@ -0,0 +1,34 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
#include <arch/exception.h>
#include <bootblock_common.h>
#include <console/console.h>
#include <program_loading.h>
// the qemu part of all this is very, very non-hardware like.
// so it gets its own bootblock.
void main(void)
{
if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) {
console_init();
exception_init();
}
run_romstage();
}

20
src/mainboard/emulation/spike-riscv/devicetree.cb Normal file
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@ -0,0 +1,20 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2014 Google, Inc.
##
## This software is licensed under the terms of the GNU General Public
## License version 2, as published by the Free Software Foundation, and
## may be copied, distributed, and modified under those terms.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
chip soc/ucb/riscv
device cpu_cluster 0 on end
chip drivers/generic/generic # I2C0 controller
device i2c 6 on end # Fake component for testing
end
end

34
src/mainboard/emulation/spike-riscv/mainboard.c Normal file
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@ -0,0 +1,34 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <device/device.h>
#include <cbmem.h>
static void mainboard_enable(device_t dev)
{
if (!dev) {
printk(BIOS_EMERG, "No dev0; die\n");
while (1);
}
ram_resource(dev, 0, 2048, 32768);
cbmem_recovery(0);
}
struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
};

32
src/mainboard/emulation/spike-riscv/memlayout.ld Normal file
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@ -0,0 +1,32 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
#include <memlayout.h>
#include <arch/header.ld>
SECTIONS
{
DRAM_START(0x0)
BOOTBLOCK(0x0, 64K)
ROMSTAGE(0x20000, 128K)
STACK(0x40000, 0x3ff00)
PRERAM_CBMEM_CONSOLE(0x80000, 8K)
RAMSTAGE(0x100000, 16M)
}

23
src/mainboard/emulation/spike-riscv/romstage.c Normal file
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@ -0,0 +1,23 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <program_loading.h>
void main(void)
{
console_init();
run_ramstage();
}

82
src/mainboard/emulation/spike-riscv/spike_util.c Normal file
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@ -0,0 +1,82 @@
#include <spike_util.h>
uintptr_t htif_interrupt(uintptr_t mcause, uintptr_t* regs) {
uintptr_t fromhost = swap_csr(mfromhost, 0);
if (!fromhost)
return 0;
uintptr_t dev = FROMHOST_DEV(fromhost);
uintptr_t cmd = FROMHOST_CMD(fromhost);
uintptr_t data = FROMHOST_DATA(fromhost);
sbi_device_message* m = HLS()->device_request_queue_head;
sbi_device_message* prev = 0x0;
unsigned long i, n;
for (i = 0, n = HLS()->device_request_queue_size; i < n; i++) {
/*
if (!supervisor_paddr_valid(m, sizeof(*m))
&& EXTRACT_FIELD(read_csr(mstatus), MSTATUS_PRV1) != PRV_M)
panic("htif: page fault");
*/
sbi_device_message* next = (void*)m->sbi_private_data;
if (m->dev == dev && m->cmd == cmd) {
m->data = data;
// dequeue from request queue
if (prev)
prev->sbi_private_data = (uintptr_t)next;
else
HLS()->device_request_queue_head = next;
HLS()->device_request_queue_size = n-1;
m->sbi_private_data = 0;
// enqueue to response queue
if (HLS()->device_response_queue_tail)
{
HLS()->device_response_queue_tail->sbi_private_data = (uintptr_t)m;
}
else
{
HLS()->device_response_queue_head = m;
}
HLS()->device_response_queue_tail = m;
// signal software interrupt
set_csr(mip, MIP_SSIP);
return 0;
}
prev = m;
m = (void*)atomic_read(&m->sbi_private_data);
}
//HLT();
return 0;
//panic("htif: no record");
}
uintptr_t mcall_console_putchar(uint8_t ch)
{
while (swap_csr(mtohost, TOHOST_CMD(1, 1, ch)) != 0);
while (1) {
uintptr_t fromhost = read_csr(mfromhost);
if (FROMHOST_DEV(fromhost) != 1 || FROMHOST_CMD(fromhost) != 1) {
if (fromhost)
htif_interrupt(0, 0);
continue;
}
write_csr(mfromhost, 0);
break;
}
return 0;
}
void testPrint(void) {
/* Print a test command to check Spike console output */
mcall_console_putchar('h');
mcall_console_putchar('e');
mcall_console_putchar('l');
mcall_console_putchar('l');
mcall_console_putchar('o');
mcall_console_putchar('\n');
}

61
src/mainboard/emulation/spike-riscv/uart.c Normal file
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@ -0,0 +1,61 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
#include <types.h>
#include <console/uart.h>
#include <arch/io.h>
#include <boot/coreboot_tables.h>
#include <spike_util.h>
static uint8_t *buf = (void *)0x3f8;
uintptr_t uart_platform_base(int idx)
{
return (uintptr_t) buf;
}
void uart_init(int idx)
{
}
unsigned char uart_rx_byte(int idx)
{
return *buf; // this does not work on spike, requires more implementation details
}
void uart_tx_byte(int idx, unsigned char data)
{
mcall_console_putchar(data);
}
void uart_tx_flush(int idx)
{
}
#ifndef __PRE_RAM__
void uart_fill_lb(void *data)
{
struct lb_serial serial;
serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
serial.baseaddr = 0x3f8;
serial.baud = 115200;
serial.regwidth = 1;
lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
}
#endif