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mb/google/brya: Fill in gpio.h for nissa baseboard 

BUG=b:197479026
TEST=abuild -a -x -c max -p none -t google/brya -b nivviks
     abuild -a -x -c max -p none -t google/brya -b nereid

Change-Id: I7ec4b9368e0a63c0c0c9a92c8367a89d57f10d51
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Reka Norman 2022-01-25 10:08:38 +11:00 committed by Felix Held
parent a69125c723
commit 8fb462fcc8
1 changed files with 10 additions and 5 deletions
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15
src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/gpio.h
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@ -6,10 +6,15 @@
#include <soc/gpe.h> #include <soc/gpe.h>
#include <soc/gpio.h> #include <soc/gpio.h>
/* TODO: Set the correct values */ /* eSPI virtual wire reporting */
#define EC_SCI_GPI 0 #define EC_SCI_GPI GPE0_ESPI
#define GPIO_PCH_WP 0 /* EC wake is EC_SOC_WAKE_ODL which is routed to GPP_F17 */
#define GPIO_EC_IN_RW 0 #define GPE_EC_WAKE GPE0_DW2_17
#define GPIO_SLP_S0_GATE 0 /* WP signal to PCH */
#define GPIO_PCH_WP GPP_E12
/* EC in RW or RO */
#define GPIO_EC_IN_RW GPP_F18
/* GPIO IRQ for tight timestamps */
#define EC_SYNC_IRQ GPD2_IRQ
#endif /* __BASEBOARD_GPIO_H__ */ #endif /* __BASEBOARD_GPIO_H__ */