opencellular/rotundu: Add mainboard support
Adds Open Cellular rotundu mainboard supports. Working: - 2x Ethernet support - MSATA support - CPU init - Memory init - USB support - EMMC but disabled Not working: - TPM support Create directory structure and Kconfig files for OpenCellular Rotundu and copy sources from intel/minnowmax. Change-Id: I391d4bdd485f4bf5396c764fe3f11d98369593e4 Signed-off-by: Hong Gan <hgan@fb.com> Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/22894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Hong Gan
Philipp Deppenwiese
parent
5f187dbe63
commit
8fb9f23d51
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2017-present Facebook, Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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if VENDOR_OPENCELLULAR
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choice
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prompt "Mainboard model"
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source "src/mainboard/opencellular/*/Kconfig.name"
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endchoice
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source "src/mainboard/opencellular/*/Kconfig"
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config MAINBOARD_VENDOR
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string
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default "OpenCellular"
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endif # VENDOR_OPENCELLULAR
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@ -0,0 +1,2 @@
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config VENDOR_OPENCELLULAR
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bool "OpenCellular"
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@ -0,0 +1,80 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
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## Copyright (C) 2014 Intel Corporation
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## Copyright (C) 2017-present Facebook, Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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if BOARD_OPENCELLULAR_ROTUNDU
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select SOC_INTEL_FSP_BAYTRAIL
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select BOARD_ROMSIZE_KB_16384
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select HAVE_ACPI_TABLES
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select HAVE_OPTION_TABLE
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select ENABLE_BUILTIN_COM1
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select TSC_MONOTONIC_TIMER
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select ENABLE_FSP_FAST_BOOT
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select HAVE_ACPI_RESUME
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select USE_BLOBS
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select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
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config MAINBOARD_DIR
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string
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default "opencellular/rotundu"
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config MAINBOARD_PART_NUMBER
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string
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default "Rotundu"
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config MAINBOARD_VENDOR
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string
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default "OpenCellular"
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config MAX_CPUS
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int
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default 16
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config CACHE_ROM_SIZE_OVERRIDE
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hex
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default 0x800000
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config FSP_LOC
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hex
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default 0xfffb0000
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# FIXME: Slow boot performance when increasing CBFS_SIZE beyond 8MB?
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config CBFS_SIZE
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hex
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default 0x00200000 if BOARD_ROMSIZE_KB_8192
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default 0x00800000
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config VIRTUAL_ROM_SIZE
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hex
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depends on ENABLE_FSP_FAST_BOOT
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default 0x800000
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config FSP_PACKAGE_DEFAULT
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bool "Configure defaults for the Intel FSP package"
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default n
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config VGA_BIOS
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bool
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default y if FSP_PACKAGE_DEFAULT
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config VGA_BIOS_ID
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string
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default "8086,0f31"
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endif # BOARD_OPENCELLULAR_ROTUNDU
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@ -0,0 +1,2 @@
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config BOARD_OPENCELLULAR_ROTUNDU
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bool "Rotundu"
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@ -0,0 +1,17 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2013 Google Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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ramstage-y += gpio.c
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ramstage-y += irqroute.c
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Google Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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Device (PWRB)
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{
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Name(_HID, EisaId("PNP0C0C"))
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}
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Google Inc.
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* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
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* Copyright (C) 2017-present Facebook, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/acpi.h>
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#include <arch/ioapic.h>
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#include <arch/acpigen.h>
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#include <arch/smp/mpspec.h>
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#include <soc/acpi.h>
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#include <soc/nvs.h>
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#include <soc/iomap.h>
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void acpi_create_gnvs(global_nvs_t *gnvs)
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{
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acpi_init_gnvs(gnvs);
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/* Enable USB ports in S3 */
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gnvs->s3u0 = 1;
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gnvs->s3u1 = 1;
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/* Disable USB ports in S5 */
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gnvs->s5u0 = 0;
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gnvs->s5u1 = 0;
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/* TPM Present */
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gnvs->tpmp = 0;
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/* Enable DPTF */
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gnvs->dpte = 0;
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}
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unsigned long acpi_fill_madt(unsigned long current)
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{
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/* Local APICs */
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current = acpi_create_madt_lapics(current);
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/* IOAPIC */
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
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2, IO_APIC_ADDR, 0);
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current = acpi_madt_irq_overrides(current);
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return current;
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}
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Board name: Rotundu
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Category: sbc
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ROM protocol: SPI
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ROM socketed: n
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@ -0,0 +1,37 @@
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FLASH@0xff800000 0x800000 {
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SI_ALL@0x0 0x300000 {
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SI_DESC@0x0 0x1000
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SI_ME@0x1000 0x2ff000
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}
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SI_BIOS@0x300000 0x500000 {
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RW_SECTION_A@0x0 0xf0000 {
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VBLOCK_A@0x0 0x10000
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FW_MAIN_A(CBFS)@0x10000 0xc0000
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RW_FWID_A@0xeffc0 0x40
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}
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RW_SECTION_B@0xf0000 0xf0000 {
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VBLOCK_B@0x0 0x10000
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FW_MAIN_B(CBFS)@0x10000 0xc0000
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RW_FWID_B@0xeffc0 0x40
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}
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RW_MRC_CACHE@0x1e0000 0x10000
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RW_ELOG@0x1f0000 0x4000
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RW_SHARED@0x1f4000 0x4000 {
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SHARED_DATA@0x0 0x2000
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VBLOCK_DEV@0x2000 0x2000
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}
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RW_VPD@0x1f8000 0x2000
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RW_UNUSED@0x1fa000 0x106000
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WP_RO@0x300000 0x200000 {
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RO_VPD@0x0 0x4000
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RO_UNUSED@0x4000 0xc000
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RO_SECTION@0x10000 0x1f0000 {
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FMAP@0x0 0x800
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RO_FRID@0x800 0x40
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RO_FRID_PAD@0x840 0x7c0
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GBB@0x1000 0xef000
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COREBOOT(CBFS)@0xf0000 0x100000
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}
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}
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}
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}
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debug_level=Error
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2008 coresystems GmbH
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## Copyright (C) 2017-present Facebook, Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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# -----------------------------------------------------------------
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entries
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# -----------------------------------------------------------------
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# Status Register A
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# -----------------------------------------------------------------
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# Status Register B
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# -----------------------------------------------------------------
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# Status Register C
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#96 4 r 0 status_c_rsvd
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#100 1 r 0 uf_flag
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#101 1 r 0 af_flag
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#102 1 r 0 pf_flag
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#103 1 r 0 irqf_flag
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# -----------------------------------------------------------------
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# Status Register D
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#104 7 r 0 status_d_rsvd
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#111 1 r 0 valid_cmos_ram
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# -----------------------------------------------------------------
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# Diagnostic Status Register
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#112 8 r 0 diag_rsvd1
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# -----------------------------------------------------------------
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0 120 r 0 reserved_memory
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#120 264 r 0 unused
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# -----------------------------------------------------------------
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 4 boot_option
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#390 2 r 0 unused?
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# -----------------------------------------------------------------
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# coreboot config options: console
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395 4 e 6 debug_level
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#399 1 r 0 unused
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# coreboot config options: cpu
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#401 7 r 0 unused
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# coreboot config options: southbridge
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408 1 e 1 nmi
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411 2 e 8 use_xhci_over_ehci
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#413 3 r 0 unused
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# MRC Scrambler Seed values
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928 32 r 0 mrc_scrambler_seed_s3
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# coreboot config options: check sums
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984 16 h 0 check_sum
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#1000 24 r 0 amd_reserved
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# -----------------------------------------------------------------
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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6 1 Emergency
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6 2 Alert
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6 3 Critical
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6 4 Error
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6 5 Warning
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6 6 Notice
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6 7 Info
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6 8 Debug
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6 9 Spew
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7 0 Disable
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7 1 Enable
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7 2 Keep
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8 0 EHCI
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8 1 XHCI
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8 2 Default
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# -----------------------------------------------------------------
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checksums
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checksum 392 415 984
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@ -0,0 +1,81 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
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## Copyright (C) 2014 Intel Corporation
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## Copyright (C) 2017-present Facebook, Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
|
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##
|
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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chip soc/intel/fsp_baytrail
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#### ACPI Register Settings ####
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register "fadt_pm_profile" = "PM_UNSPECIFIED"
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register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE"
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#### FSP register settings ####
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register "PcdSataMode" = "SATA_MODE_AHCI"
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register "PcdMrcInitSPDAddr1" = "0xa0"
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register "PcdMrcInitSPDAddr2" = "0xa2"
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register "PcdMrcInitMmioSize" = "MMIO_SIZE_DEFAULT"
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register "PcdeMMCBootMode" = "EMMC_DISABLED"
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register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT"
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register "PcdApertureSize" = "APERTURE_SIZE_DEFAULT"
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register "PcdGttSize" = "GTT_SIZE_DEFAULT"
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register "PcdLpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT"
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register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE"
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register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED"
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register "EnableMemoryDown" = "MEMORY_DOWN_DISABLE"
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register "DIMM0Enable" = "DIMM0_ENABLE"
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register "DIMM1Enable" = "DIMM1_DISABLE"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 on end # 8086 0F00 - SoC router
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device pci 02.0 on end # 8086 0F31 - GFX
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device pci 03.0 off end # 8086 0F38 - MIPI - camera interface
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device pci 10.0 off end # 8086 0F14 - EMMC 4.1 Port (MMC1 pins) - (DO NOT USE) - Only 1 EMMC port at a time
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device pci 11.0 off end # 8086 0F15 - SDIO Port (SD2 pins)
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device pci 12.0 off end # 8086 0F16 - SD Port (SD3 pins)
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device pci 13.0 on end # 8086 0F23 - SATA AHCI (0F20, 0F21, 0F22, 0F23)
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device pci 14.0 on end # 8086 0F35 - USB XHCI - Only 1 USB controller at a time
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device pci 15.0 off end # 8086 0F28 - LP Engine Audio
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device pci 16.0 off end # 8086 0F37 - OTG controller
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device pci 17.0 off end # 8086 0F50 - EMMC 4.5 Port (MMC1 pins) - Only 1 EMMC port at a time
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device pci 18.0 on end # 8086 0F40 - SIO - DMA
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device pci 18.1 on end # 8086 0F41 - I2C Port 1
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device pci 18.2 off end # 8086 0F42 - I2C Port 2
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device pci 18.3 on end # 8086 0F43 - I2C Port 3
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device pci 18.4 off end # 8086 0F44 - I2C Port 4
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device pci 18.5 off end # 8086 0F45 - I2C Port 5
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device pci 18.6 off end # 8086 0F46 - I2C Port 6
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device pci 18.7 off end # 8086 0F47 - I2C Port 7
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device pci 1a.0 on end # 8086 0F18 - Trusted Execution Engine
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device pci 1b.0 off end # 8086 0F04 - HD Audio
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device pci 1c.0 on end # 8086 0F48 - PCIe Root Port 1 (RADIO CARD)
|
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device pci 1c.1 on end # 8086 0F4A - PCIe Root Port 2 (GBE PHY 1)
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device pci 1c.2 on end # 8086 0F4C - PCIe Root Port 3 (GBE PHY 2)
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device pci 1c.3 off end # 8086 0F4E - PCIe Root Port 4 (NC)
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device pci 1d.0 off end # 8086 0F34 - USB EHCI - Only 1 USB controller at a time
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device pci 1e.0 on end # 8086 0F06 - SIO - DMA
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device pci 1e.1 off end # 8086 0F08 - PWM 1
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device pci 1e.2 off end # 8086 0F09 - PWM 2
|
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device pci 1e.3 on end # 8086 0F0A - HSUART 1
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device pci 1e.4 off end # 8086 0F0C - HSUART 2
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device pci 1e.5 off end # 8086 0F0E - SPI
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device pci 1f.0 on end # 8086 0F1C - LPC bridge
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||||
device pci 1f.3 on end # 8086 0F12 - SMBus 0
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end
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end
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@ -0,0 +1,53 @@
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/*
|
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* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2011 Google Inc.
|
||||
* Copyright (C) 2014 Sage Electronic Engineering, LLC.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#define INCLUDE_LPE 1
|
||||
#define INCLUDE_SCC 1
|
||||
#define INCLUDE_EHCI 1
|
||||
#define INCLUDE_XHCI 1
|
||||
#define INCLUDE_LPSS 1
|
||||
|
||||
|
||||
DefinitionBlock(
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
0x02, // DSDT revision: ACPI v2.0
|
||||
"COREv4", // OEM id
|
||||
"COREBOOT", // OEM table id
|
||||
0x20110725 // OEM revision
|
||||
)
|
||||
{
|
||||
// Some generic macros
|
||||
#include <soc/intel/fsp_baytrail/acpi/platform.asl>
|
||||
|
||||
// global NVS and variables
|
||||
#include <soc/intel/fsp_baytrail/acpi/globalnvs.asl>
|
||||
|
||||
#include <soc/intel/fsp_baytrail/acpi/cpu.asl>
|
||||
|
||||
Scope (\_SB) {
|
||||
Device (PCI0)
|
||||
{
|
||||
#include <soc/intel/fsp_baytrail/acpi/southcluster.asl>
|
||||
}
|
||||
}
|
||||
|
||||
/* Chipset specific sleep states */
|
||||
#include <soc/intel/fsp_baytrail/acpi/sleepstates.asl>
|
||||
|
||||
#include "acpi/mainboard.asl"
|
||||
}
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/acpi.h>
|
||||
#include <soc/acpi.h>
|
||||
|
||||
void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
|
||||
{
|
||||
acpi_header_t *header = &(fadt->header);
|
||||
|
||||
acpi_fill_in_fadt(fadt, facs, dsdt);
|
||||
|
||||
/* Platform specific customizations go here */
|
||||
|
||||
header->checksum = 0;
|
||||
header->checksum =
|
||||
acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,362 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2013 Google Inc.
|
||||
* Copyright (C) 2014 Sage Electronic Engineering, LLC.
|
||||
* Copyright (C) 2017-present Facebook, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <soc/gpio.h>
|
||||
#include "irqroute.h"
|
||||
|
||||
/* NCORE GPIOs */
|
||||
static const struct soc_gpio_map gpncore_gpio_map[] = {
|
||||
|
||||
GPIO_FUNC2, /* GPIO 0 */
|
||||
GPIO_FUNC2, /* GPIO 1 */
|
||||
GPIO_FUNC2, /* GPIO 2 */
|
||||
GPIO_FUNC2, /* GPIO 3 */
|
||||
GPIO_FUNC2, /* GPIO 4 */
|
||||
GPIO_FUNC2, /* GPIO 5 */
|
||||
GPIO_FUNC2, /* GPIO 6 */
|
||||
GPIO_FUNC2, /* GPIO 7 */
|
||||
GPIO_FUNC2, /* GPIO 8 */
|
||||
GPIO_FUNC2, /* GPIO 9 */
|
||||
GPIO_FUNC2, /* GPIO 10 */
|
||||
GPIO_FUNC2, /* GPIO 11 */
|
||||
GPIO_FUNC2, /* GPIO 12 */
|
||||
GPIO_FUNC2, /* GPIO 13 */
|
||||
GPIO_FUNC2, /* GPIO 14 */
|
||||
GPIO_FUNC2, /* GPIO 15 */
|
||||
GPIO_FUNC2, /* GPIO 16 */
|
||||
GPIO_FUNC2, /* GPIO 17 */
|
||||
GPIO_FUNC2, /* GPIO 18 */
|
||||
GPIO_FUNC2, /* GPIO 19 */
|
||||
GPIO_FUNC2, /* GPIO 20 */
|
||||
GPIO_FUNC2, /* GPIO 21 */
|
||||
GPIO_FUNC2, /* GPIO 22 */
|
||||
GPIO_FUNC2, /* GPIO 23 */
|
||||
GPIO_FUNC2, /* GPIO 24 */
|
||||
GPIO_FUNC2, /* GPIO 25 */
|
||||
GPIO_FUNC2, /* GPIO 26 */
|
||||
GPIO_END};
|
||||
|
||||
/* SCORE GPIOs (GPIO_S0_SC_XX) */
|
||||
static const struct soc_gpio_map gpscore_gpio_map[] = {
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[000] SATA_GP[0] */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[001] SATA_GP[1] SATA_DEVSLP[0]*/
|
||||
GPIO_FUNC1,
|
||||
/* GPIO_S0_SC[002] SATA_LED# */
|
||||
GPIO_FUNC1,
|
||||
/* GPIO_S0_SC[003] PCIE_CLKREQ[0]# */
|
||||
GPIO_FUNC1,
|
||||
/* GPIO_S0_SC[004] PCIE_CLKREQ[1]# */
|
||||
GPIO_FUNC1,
|
||||
/* GPIO_S0_SC[005] PCIE_CLKREQ[2]# */
|
||||
GPIO_FUNC1,
|
||||
/* GPIO_S0_SC[006] PCIE_CLKREQ[3]# */
|
||||
GPIO_FUNC2,
|
||||
/* GPIO_S0_SC[007] RESERVED SD3_WP */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[008] I2S0_CLK HDA_RST#*/
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[009] I2S0_FRM HDA_SYNC*/
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[010] I2S0_DATAOUT HDA_CLK */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[011] I2S0_DATAIN HDA_SDO */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[012] I2S1_CLK HDA_SDI[0]*/
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[013] I2S1_FRM HDA_SDI[1]*/
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[014] I2S1_DATAOUT RESERVED*/
|
||||
GPIO_DEFAULT,
|
||||
/* GPIO_S0_SC[015] I2S1_DATAIN RESERVED*/
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[016] MMC1_CLK MMC1_45_CLK */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[017] MMC1_D[0] MMC1_45_D[0] */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[018] MMC1_D[1] MMC1_45_D[1] */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[019] MMC1_D[2] MMC1_45_D[2] */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[020] MMC1_D[3] MMC1_45_D[3] */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[021] MMC1_D[4] MMC1_45_D[4] */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[022] MMC1_D[5] MMC1_45_D[5] */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[023] MMC1_D[6] MMC1_45_D[6] */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[024] MMC1_D[7] MMC1_45_D[7] */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[025] MMC1_CMD MMC1_45_CMD */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[026] MMC1_RST# SATA_DEVSLP[0] MMC1_45_RST# */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[027] SD2_CLK */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[028] SD2_D[0] */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[029] SD2_D[1] */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[030] SD2_D[2] */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[031] SD2_D[3]_CD# */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[032] SD2_CMD */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[033] SD3_CLK */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[034] SD3_D[0] */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[035] SD3_D[1] */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[036] SD3_D[2] */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[037] SD3_D[3] */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[038] SD3_CD# */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[039] SD3_CMD */
|
||||
GPIO_FUNC1,
|
||||
/* GPIO_S0_SC[040] SD3_1P8EN */
|
||||
GPIO_FUNC1,
|
||||
/* GPIO_S0_SC[041] SD3_PWREN# */
|
||||
GPIO_FUNC1,
|
||||
/* GPIO_S0_SC[042] ILB_LPC_AD[0] */
|
||||
GPIO_FUNC1,
|
||||
/* GPIO_S0_SC[043] ILB_LPC_AD[1] */
|
||||
GPIO_FUNC1,
|
||||
/* GPIO_S0_SC[044] ILB_LPC_AD[2] */
|
||||
GPIO_FUNC1,
|
||||
/* GPIO_S0_SC[045] ILB_LPC_AD[3] */
|
||||
GPIO_FUNC1,
|
||||
/* GPIO_S0_SC[046] ILB_LPC_FRAME# */
|
||||
GPIO_FUNC1,
|
||||
/* GPIO_S0_SC[047] ILB_LPC_CLK[0] */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[048] ILB_LPC_CLK[1] */
|
||||
GPIO_FUNC1,
|
||||
/* GPIO_S0_SC[049] ILB_LPC_CLKRUN# */
|
||||
GPIO_FUNC1,
|
||||
/* GPIO_S0_SC[050] ILB_LPC_SERIRQ */
|
||||
GPIO_FUNC1,
|
||||
/* GPIO_S0_SC[051] PCU_SMB_DATA */
|
||||
GPIO_FUNC1,
|
||||
/* GPIO_S0_SC[052] PCU_SMB_CLK */
|
||||
GPIO_FUNC1,
|
||||
/* GPIO_S0_SC[053] PCU_SMB_ALERT# */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[054] ILB_8254_SPKR RESERVED*/
|
||||
GPIO_DEFAULT,
|
||||
/* GPIO_S0_SC[055] RESERVED */
|
||||
GPIO_DEFAULT,
|
||||
/* GPIO_S0_SC[056] RESERVED */
|
||||
GPIO_FUNC1,
|
||||
/* GPIO_S0_SC[057] PCU_UART_TXD */
|
||||
GPIO_DEFAULT,
|
||||
/* GPIO_S0_SC[058] RESERVED */
|
||||
GPIO_DEFAULT,
|
||||
/* GPIO_S0_SC[059] RESERVED */
|
||||
GPIO_DEFAULT,
|
||||
/* GPIO_S0_SC[060] RESERVED */
|
||||
GPIO_FUNC1,
|
||||
/* GPIO_S0_SC[061] PCU_UART_RXD */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[062] LPE_I2S2_CLK SATA_DEVSLP[1] RESERVED */
|
||||
GPIO_FUNC1,
|
||||
/* GPIO_S0_SC[063] LPE_I2S2_FRM RESERVED*/
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[064] LPE_I2S2_DATAIN */
|
||||
GPIO_FUNC1,
|
||||
/* GPIO_S0_SC[065] LPE_I2S2_DATAOUT*/
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[066] SIO_SPI_CS# */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[067] SIO_SPI_MISO */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[068] SIO_SPI_MOSI */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[069] SIO_SPI_CLK */
|
||||
GPIO_FUNC1,
|
||||
/* GPIO_S0_SC[070] SIO_UART1_RXD RESERVED*/
|
||||
GPIO_FUNC1,
|
||||
/* GPIO_S0_SC[071] SIO_UART1_TXD RESERVED*/
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[072] SIO_UART1_RTS# */
|
||||
GPIO_DEFAULT,
|
||||
/* GPIO_S0_SC[073] SIO_UART1_CTS# */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[074] SIO_UART2_RXD */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[075] SIO_UART2_TXD */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[076] SIO_UART2_RTS# */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[077] SIO_UART2_CTS# */
|
||||
GPIO_FUNC1,
|
||||
/* GPIO_S0_SC[078] SIO_I2C0_DATA */
|
||||
GPIO_FUNC1,
|
||||
/* GPIO_S0_SC[079] SIO_I2C0_CLK */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[080] SIO_I2C1_DATA */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[081] SIO_I2C1_CLK RESERVED*/
|
||||
GPIO_FUNC1,
|
||||
/* GPIO_S0_SC[082] SIO_I2C2_DATA */
|
||||
GPIO_FUNC1,
|
||||
/* GPIO_S0_SC[083] SIO_I2C2_CLK */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[084] SIO_I2C3_DATA */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[085] SIO_I2C3_CLK */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[086] SIO_I2C4_DATA */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[087] SIO_I2C4_CLK */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[088] SIO_I2C5_DATA */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[089] SIO_I2C5_CLK */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[090] SIO_I2C6_DATA ILB_NMI */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[091] SIO_I2C6_CLK SD3_WP */
|
||||
GPIO_NC,
|
||||
/* RESERVED GPIO_S0_SC[092] */
|
||||
GPIO_NC,
|
||||
/* RESERVED GPIO_S0_SC[093] */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[094] SIO_PWM[0] */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[095] SIO_PWM[1] */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[096] PMC_PLT_CLK[0] */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[097] PMC_PLT_CLK[1] */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[098] PMC_PLT_CLK[2] */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[099] PMC_PLT_CLK[3] */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[100] PMC_PLT_CLK[4] */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[101] PMC_PLT_CLK[5]*/
|
||||
GPIO_END};
|
||||
|
||||
/* SSUS GPIOs (GPIO_S5) */
|
||||
static const struct soc_gpio_map gpssus_gpio_map[] = {
|
||||
GPIO_DEFAULT,
|
||||
/* GPIO_S5[00] RESERVED- */
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[01] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[1]# */
|
||||
GPIO_DEFAULT,
|
||||
/* GPIO_S5[02] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[2]# */
|
||||
GPIO_DEFAULT,
|
||||
/* GPIO_S5[03] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[3]# */
|
||||
GPIO_DEFAULT,
|
||||
/* GPIO_S5[04] RESERVED RESERVED RESERVED RESERVED */
|
||||
GPIO_DEFAULT,
|
||||
/* GPIO_S5[05] PMC_SUSCLK[1] RESERVED RESERVED RESERVED */
|
||||
GPIO_DEFAULT,
|
||||
/* GPIO_S5[06] PMC_SUSCLK[2] RESERVED RESERVED RESERVED */
|
||||
GPIO_DEFAULT,
|
||||
/* GPIO_S5[07] PMC_SUSCLK[3] RESERVED RESERVED RESERVED */
|
||||
GPIO_DEFAULT,
|
||||
/* GPIO_S5[08] RESERVED RESERVED RESERVED RESERVED */
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[09] RESERVED RESERVED RESERVED RESERVED */
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[10] RESERVED RESERVED RESERVED*/
|
||||
GPIO_DEFAULT,
|
||||
/* PMC_SUSPWRDNACK GPIO_S5[11]*/
|
||||
GPIO_NC,
|
||||
/* PMC_SUSCLK[0] GPIO_S5[12]*/
|
||||
GPIO_NC,
|
||||
/* RESERVED GPIO_S5[13]*/
|
||||
GPIO_FUNC2,
|
||||
/* RESERVED GPIO_S5[14] USB_ULPI_RST#*/
|
||||
GPIO_FUNC0,
|
||||
/* PMC_WAKE_PCIE[0]# GPIO_S5[15]*/
|
||||
GPIO_FUNC0,
|
||||
/* PMC_PWRBTN# GPIO_S5[16]*/
|
||||
GPIO_FUNC1,
|
||||
/* RESERVED GPIO_S5[17]*/
|
||||
GPIO_FUNC0,
|
||||
/* PMC_SUS_STAT# GPIO_S5[18]*/
|
||||
GPIO_FUNC0,
|
||||
/* USB_OC[0]# GPIO_S5[19]*/
|
||||
GPIO_FUNC0,
|
||||
/* USB_OC[1]# GPIO_S5[20]*/
|
||||
GPIO_NC,
|
||||
/* PCU_SPI_CS[1]# GPIO_S5[21]*/
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[22] RESERVED RESERVED RESERVED RESERVED */
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[23] RESERVED RESERVED RESERVED RESERVED */
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[24] RESERVED RESERVED RESERVED RESERVED */
|
||||
GPIO_DEFAULT,
|
||||
/* GPIO_S5[25] RESERVED RESERVED RESERVED RESERVED */
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[26] RESERVED RESERVED RESERVED RESERVED */
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[27] RESERVED RESERVED RESERVED RESERVED */
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[28] RESERVED RESERVED RESERVED RESERVED */
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[29] RESERVED RESERVED RESERVED RESERVED */
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[30] RESERVED RESERVED RESERVED RESERVED */
|
||||
GPIO_FUNC1,
|
||||
/* GPIO_S5[31] USB_ULPI_CLK RESERVED RESERVED*/
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[32] USB_ULPI_DATA[0] RESERVED RESERVED*/
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[33] USB_ULPI_DATA[1] RESERVED RESERVED*/
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[34] USB_ULPI_DATA[2] RESERVED RESERVED*/
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[35] USB_ULPI_DATA[3] RESERVED RESERVED*/
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[36] USB_ULPI_DATA[4] RESERVED RESERVED*/
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[37] USB_ULPI_DATA[5] RESERVED RESERVED*/
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[38] USB_ULPI_DATA[6] RESERVED RESERVED*/
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[39] USB_ULPI_DATA[7] RESERVED RESERVED*/
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[40] USB_ULPI_DIR RESERVED RESERVED*/
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[41] USB_ULPI_NXT RESERVED RESERVED*/
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[42] USB_ULPI_STP RESERVED RESERVED*/
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[43] USB_ULPI_REFCLK RESERVED RESERVED*/
|
||||
GPIO_END};
|
||||
|
||||
static struct soc_gpio_config gpio_config = {
|
||||
.ncore = gpncore_gpio_map,
|
||||
.score = gpscore_gpio_map,
|
||||
.ssus = gpssus_gpio_map,
|
||||
.core_dirq = NULL,
|
||||
.sus_dirq = NULL,
|
||||
};
|
||||
|
||||
struct soc_gpio_config *mainboard_get_gpios(void) { return &gpio_config; }
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2013 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include "irqroute.h"
|
||||
|
||||
DEFINE_IRQ_ROUTES;
|
||||
|
|
@ -0,0 +1,84 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2013 Google Inc.
|
||||
* Copyright (C) 2014 Sage Electronic Engineering, LLC.
|
||||
* Copyright (C) 2017-present Facebook, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef IRQROUTE_H
|
||||
#define IRQROUTE_H
|
||||
|
||||
#include <soc/intel/fsp_baytrail/include/soc/irq.h>
|
||||
#include <soc/intel/fsp_baytrail/include/soc/pci_devs.h>
|
||||
|
||||
/*
|
||||
*IR02h GFX INT(A) - PIRQ A
|
||||
*IR10h EMMC INT(ABCD) - PIRQ DEFG
|
||||
*IR11h SDIO INT(A) - PIRQ B
|
||||
*IR12h SD INT(A) - PIRQ C
|
||||
*IR13h SATA INT(A) - PIRQ D
|
||||
*IR14h XHCI INT(A) - PIRQ E
|
||||
*IR15h LP Audio INT(A) - PIRQ F
|
||||
*IR17h MMC INT(A) - PIRQ F
|
||||
*IR18h SIO INT(ABCD) - PIRQ BADC
|
||||
*IR1Ah TXE INT(A) - PIRQ F
|
||||
*IR1Bh HD Audio INT(A) - PIRQ G
|
||||
*IR1Ch PCIe INT(ABCD) - PIRQ EFGH
|
||||
*IR1Dh EHCI INT(A) - PIRQ D
|
||||
*IR1Eh SIO INT(ABCD) - PIRQ BDEF
|
||||
*IR1Fh LPC INT(ABCD) - PIRQ HGBC
|
||||
*/
|
||||
|
||||
/* PCIe bridge routing */
|
||||
#define BRIDGE1_DEV PCIE_DEV
|
||||
|
||||
/* PCI bridge IRQs need to be updated in both tables and need to match */
|
||||
#define PCIE_BRIDGE_IRQ_ROUTES \
|
||||
PCIE_BRIDGE_DEV(RP, BRIDGE1_DEV, E, F, G, H)
|
||||
|
||||
/* Devices set as A, A, A, A evaluate as 0, and don't get set */
|
||||
#define PCI_DEV_PIRQ_ROUTES \
|
||||
PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, B), \
|
||||
PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \
|
||||
PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \
|
||||
PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \
|
||||
PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \
|
||||
PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \
|
||||
PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \
|
||||
PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \
|
||||
PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \
|
||||
PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \
|
||||
PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \
|
||||
PCI_DEV_PIRQ_ROUTE(BRIDGE1_DEV, E, F, G, H), \
|
||||
PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \
|
||||
PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \
|
||||
PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C)
|
||||
|
||||
/*
|
||||
* Route each PIRQ[A-H] to a PIC IRQ[0-15]
|
||||
* Reserved: 0, 1, 2, 8, 13
|
||||
* PS2 keyboard: 12
|
||||
* ACPI/SCI: 9
|
||||
* Floppy: 6
|
||||
*/
|
||||
#define PIRQ_PIC_ROUTES \
|
||||
PIRQ_PIC(A, 4), \
|
||||
PIRQ_PIC(B, 5), \
|
||||
PIRQ_PIC(C, 7), \
|
||||
PIRQ_PIC(D, 10), \
|
||||
PIRQ_PIC(E, 11), \
|
||||
PIRQ_PIC(F, 12), \
|
||||
PIRQ_PIC(G, 14), \
|
||||
PIRQ_PIC(H, 15)
|
||||
|
||||
#endif /* IRQROUTE_H */
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
|
||||
* Copyright (C) 2014 Sage Electronic Engineering, LLC
|
||||
* Copyright (C) 2017-present Facebook, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <device/device.h>
|
||||
|
||||
/*
|
||||
* mainboard_enable is executed as first thing after enumerate_buses().
|
||||
* This is the earliest point to add customization.
|
||||
*/
|
||||
static void mainboard_enable(struct device *dev)
|
||||
{
|
||||
}
|
||||
|
||||
/*
|
||||
* mainboard_final is executed as one of the last items before loading the
|
||||
* payload.
|
||||
*
|
||||
* This is the latest point to add customization.
|
||||
*/
|
||||
static void mainboard_final(void *chip_info)
|
||||
{
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
.final = mainboard_final,
|
||||
};
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2013 Google Inc.
|
||||
* Copyright (C) 2013 Sage Electronic Engineering, LLC.
|
||||
* Copyright (C) 2014 Intel Corporation
|
||||
* Copyright (C) 2017-present Facebook, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <soc/gpio.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <drivers/intel/fsp1_0/fsp_util.h>
|
||||
#include <soc/intel/fsp_baytrail/chip.h>
|
||||
|
||||
/**
|
||||
* /brief mainboard call for setup that needs to be done before fsp init
|
||||
*
|
||||
*/
|
||||
void early_mainboard_romstage_entry(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* Get function disables - most of these will be done automatically
|
||||
* @param fd_mask
|
||||
* @param fd2_mask
|
||||
*/
|
||||
void get_func_disables(uint32_t *fd_mask, uint32_t *fd2_mask)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* /brief mainboard call for setup that needs to be done after fsp init
|
||||
*
|
||||
*/
|
||||
void late_mainboard_romstage_entry(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
|
||||
{
|
||||
printk(BIOS_NOTICE, "This is the OpenCellular Rotundu GBC board.\n");
|
||||
}
|
||||
Loading…
Reference in New Issue