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soc/intel/alderlake: add MaxDramSpeed config 

This change add MaxDramSpeed for variants usage to config dram speed.

Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: Iba0fae0ab4ff0121dc63af792458492eeb21ec2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Casper Chang 2021-09-22 22:35:54 -04:00 committed by Tim Wawrzynczak
parent 28e2945ab1
commit 8fcefd3f6f
2 changed files with 4 additions and 0 deletions
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2
src/soc/intel/alderlake/chip.h
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@ -436,6 +436,8 @@ struct soc_intel_alderlake_config {
* 0 = VR_DOMAIN_IA Core 1 = VR_DOMAIN_GT. * 0 = VR_DOMAIN_IA Core 1 = VR_DOMAIN_GT.
*/ */
struct vr_config domain_vr_config[NUM_VR_DOMAINS]; struct vr_config domain_vr_config[NUM_VR_DOMAINS];
uint16_t MaxDramSpeed;
}; };
typedef struct soc_intel_alderlake_config config_t; typedef struct soc_intel_alderlake_config config_t;

2
src/soc/intel/alderlake/romstage/fsp_params.c
View File

@ -136,6 +136,8 @@ static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg,
{ {
m_cfg->SaGv = config->SaGv; m_cfg->SaGv = config->SaGv;
m_cfg->RMT = config->RMT; m_cfg->RMT = config->RMT;
if (config->MaxDramSpeed)
m_cfg->DdrFreqLimit = config->MaxDramSpeed;
} }
static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg, static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg,