libpayload/xhci: Document struct offsets on xhci_t
This makes it easier to know what offset each register references. BUG=b:76831439 TEST=none Change-Id: I92dcbd463ceb4dd8edbbd97b51a4e9aa32a983a6 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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@ -325,16 +325,16 @@ typedef struct xhci {
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/* capreg is read-only, so no need for volatile,
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/* capreg is read-only, so no need for volatile,
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and thus 32bit accesses can be assumed. */
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and thus 32bit accesses can be assumed. */
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struct capreg {
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struct capreg {
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u8 caplength;
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u8 caplength; /* 0x00 */
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u8 res1;
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u8 res1; /* 0x01 */
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union {
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union { /* 0x02 */
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u16 hciversion;
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u16 hciversion;
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struct {
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struct {
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u8 hciver_lo;
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u8 hciver_lo;
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u8 hciver_hi;
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u8 hciver_hi;
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} __packed;
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} __packed;
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} __packed;
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} __packed;
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union {
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union { /* 0x04 */
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u32 hcsparams1;
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u32 hcsparams1;
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struct {
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struct {
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unsigned long MaxSlots:7;
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unsigned long MaxSlots:7;
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@ -343,7 +343,7 @@ typedef struct xhci {
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unsigned long MaxPorts:8;
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unsigned long MaxPorts:8;
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} __packed;
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} __packed;
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} __packed;
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} __packed;
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union {
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union { /* 0x08 */
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u32 hcsparams2;
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u32 hcsparams2;
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struct {
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struct {
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unsigned long IST:4;
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unsigned long IST:4;
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@ -354,7 +354,7 @@ typedef struct xhci {
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unsigned long Max_Scratchpad_Bufs_Lo:5;
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unsigned long Max_Scratchpad_Bufs_Lo:5;
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} __packed;
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} __packed;
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} __packed;
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} __packed;
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union {
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union { /* 0x0C */
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u32 hcsparams3;
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u32 hcsparams3;
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struct {
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struct {
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unsigned long u1latency:8;
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unsigned long u1latency:8;
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@ -362,7 +362,7 @@ typedef struct xhci {
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unsigned long u2latency:16;
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unsigned long u2latency:16;
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} __packed;
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} __packed;
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} __packed;
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} __packed;
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union {
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union { /* 0x10 */
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u32 hccparams;
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u32 hccparams;
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struct {
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struct {
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unsigned long ac64:1;
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unsigned long ac64:1;
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@ -378,42 +378,42 @@ typedef struct xhci {
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unsigned long xECP:16;
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unsigned long xECP:16;
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} __packed;
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} __packed;
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} __packed;
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} __packed;
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u32 dboff;
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u32 dboff; /* 0x14 */
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u32 rtsoff;
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u32 rtsoff; /* 0x18 */
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} __packed *capreg;
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} __packed *capreg;
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/* opreg is R/W is most places, so volatile access is necessary.
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/* opreg is R/W is most places, so volatile access is necessary.
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volatile means that the compiler seeks byte writes if possible,
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volatile means that the compiler seeks byte writes if possible,
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making bitfields unusable for MMIO register blocks. Yay C :-( */
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making bitfields unusable for MMIO register blocks. Yay C :-( */
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volatile struct opreg {
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volatile struct opreg {
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u32 usbcmd;
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u32 usbcmd; /* 0x00 */
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#define USBCMD_RS (1 << 0)
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#define USBCMD_RS (1 << 0)
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#define USBCMD_HCRST (1 << 1)
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#define USBCMD_HCRST (1 << 1)
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#define USBCMD_INTE (1 << 2)
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#define USBCMD_INTE (1 << 2)
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u32 usbsts;
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u32 usbsts; /* 0x04 */
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#define USBSTS_HCH (1 << 0)
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#define USBSTS_HCH (1 << 0)
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#define USBSTS_HSE (1 << 2)
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#define USBSTS_HSE (1 << 2)
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#define USBSTS_EINT (1 << 3)
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#define USBSTS_EINT (1 << 3)
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#define USBSTS_PCD (1 << 4)
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#define USBSTS_PCD (1 << 4)
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#define USBSTS_CNR (1 << 11)
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#define USBSTS_CNR (1 << 11)
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#define USBSTS_PRSRV_MASK ((1 << 1) | 0xffffe000)
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#define USBSTS_PRSRV_MASK ((1 << 1) | 0xffffe000)
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u32 pagesize;
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u32 pagesize; /* 0x08 */
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u8 res1[0x13-0x0c+1];
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u8 res1[0x13-0x0c+1]; /* 0x0C */
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u32 dnctrl;
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u32 dnctrl; /* 0x14 */
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u32 crcr_lo;
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u32 crcr_lo; /* 0x18 */
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u32 crcr_hi;
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u32 crcr_hi; /* 0x1C */
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#define CRCR_RCS (1 << 0)
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#define CRCR_RCS (1 << 0)
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#define CRCR_CS (1 << 1)
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#define CRCR_CS (1 << 1)
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#define CRCR_CA (1 << 2)
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#define CRCR_CA (1 << 2)
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#define CRCR_CRR (1 << 3)
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#define CRCR_CRR (1 << 3)
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u8 res2[0x2f-0x20+1];
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u8 res2[0x2f-0x20+1]; /* 0x20 */
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u32 dcbaap_lo;
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u32 dcbaap_lo; /* 0x30 */
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u32 dcbaap_hi;
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u32 dcbaap_hi; /* 0x34 */
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u32 config;
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u32 config; /* 0x38 */
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#define CONFIG_LP_MASK_MaxSlotsEn 0xff
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#define CONFIG_LP_MASK_MaxSlotsEn 0xff
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u8 res3[0x3ff-0x3c+1];
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u8 res3[0x3ff-0x3c+1]; /* 0x3C */
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struct {
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struct {
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u32 portsc;
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u32 portsc; /* 0x400 + 4 * port */
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#define PORTSC_CCS (1 << 0)
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#define PORTSC_CCS (1 << 0)
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#define PORTSC_PED (1 << 1)
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#define PORTSC_PED (1 << 1)
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// BIT 2 rsvdZ
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// BIT 2 rsvdZ
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@ -443,9 +443,9 @@ typedef struct xhci {
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#define PORTSC_DR (1 << 30)
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#define PORTSC_DR (1 << 30)
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#define PORTSC_WPR (1 << 31)
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#define PORTSC_WPR (1 << 31)
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#define PORTSC_RW_MASK (PORTSC_PR | PORTSC_PLS_MASK | PORTSC_PP | PORTSC_PIC_MASK | PORTSC_LWS | PORTSC_WCE | PORTSC_WDE | PORTSC_WOE)
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#define PORTSC_RW_MASK (PORTSC_PR | PORTSC_PLS_MASK | PORTSC_PP | PORTSC_PIC_MASK | PORTSC_LWS | PORTSC_WCE | PORTSC_WDE | PORTSC_WOE)
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u32 portpmsc;
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u32 portpmsc; /* 0x404 + 4 * port */
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u32 portli;
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u32 portli; /* 0x408 + 4 * port */
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u32 res;
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u32 res; /* 0x40C + 4 * port */
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} __packed prs[];
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} __packed prs[];
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} __packed *opreg;
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} __packed *opreg;
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