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nb/intel/sandybridge: Move boot_count_increment() 

Move boot_count_increment() to romstage.c, drop preprocessor code and
only increase counter once on regular boot.

Tested on Lenovo T520 (Intel Sandy Bridge).
Still boots to OS, no errors visible in dmesg.

Change-Id: I6aa52b75edf19953405b70284c7e7db30f607cd6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32067
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Patrick Rudolph 2019-03-25 09:53:23 +01:00 committed by Patrick Georgi
parent 5709e03613
commit 9005071c5f
2 changed files with 5 additions and 17 deletions
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18
src/northbridge/intel/sandybridge/early_init.c
View File

@ -20,7 +20,6 @@
#include <arch/io.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <elog.h>
#include <pc80/mc146818rtc.h>
#include <romstage_handoff.h>
#include "sandybridge.h"
@ -45,22 +44,7 @@ static void sandybridge_setup_bars(void)
pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33);
pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33);
#if CONFIG(ELOG_BOOT_COUNT)
/* Increment Boot Counter for non-S3 resume */
if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&
((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3)
boot_count_increment();
#endif
printk(BIOS_DEBUG, " done.\n");
#if CONFIG(ELOG_BOOT_COUNT)
/* Increment Boot Counter except when resuming from S3 */
if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&
((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3)
return;
boot_count_increment();
#endif
printk(BIOS_DEBUG, " done\n");
}
static void sandybridge_setup_graphics(void)

4
src/northbridge/intel/sandybridge/romstage.c
View File

@ -30,6 +30,7 @@
#include <northbridge/intel/sandybridge/chip.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/pmclib.h>
#include <elog.h>
static void early_pch_reset_pmcon(void)
{
@ -79,6 +80,9 @@ void mainboard_romstage_entry(unsigned long bist)
s3resume = southbridge_detect_s3_resume();
if (CONFIG(ELOG_BOOT_COUNT) && !s3resume)
boot_count_increment();
post_code(0x38);
mainboard_early_init(s3resume);