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mb/asus/p8h61-m_pro: Switch to overridetree setup 

Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8H61-M PRO
remains identical when not adding the .config file in it.

Change-Id: I443d3823e32a246a89ff12e52a0301b2c252e23b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54388
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2021-05-17 16:12:17 +02:00 committed by Patrick Georgi
parent 945fe766a1
commit 901354b9f0
2 changed files with 4 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/mainboard/asus/h61-series/Kconfig
View File

@ -33,14 +33,14 @@ config MAINBOARD_PART_NUMBER
default "P8H61-M PRO" if BOARD_ASUS_P8H61_M_PRO default "P8H61-M PRO" if BOARD_ASUS_P8H61_M_PRO
# TODO: remove once all boards use overridetrees # TODO: remove once all boards use overridetrees
if BOARD_ASUS_P8H61_M_LX3_R2_0 if BOARD_ASUS_P8H61_M_LX3_R2_0 || BOARD_ASUS_P8H61_M_PRO
config OVERRIDE_DEVICETREE config OVERRIDE_DEVICETREE
string string
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
endif endif
if !BOARD_ASUS_P8H61_M_LX3_R2_0 if !BOARD_ASUS_P8H61_M_LX3_R2_0 && !BOARD_ASUS_P8H61_M_PRO
config DEVICETREE config DEVICETREE
string string

33
src/mainboard/asus/h61-series/variants/p8h61-m_pro/devicetree.cb → src/mainboard/asus/h61-series/variants/p8h61-m_pro/overridetree.cb
View File

@ -1,34 +1,10 @@
## SPDX-License-Identifier: GPL-2.0-or-later ## SPDX-License-Identifier: GPL-2.0-or-later
chip northbridge/intel/sandybridge chip northbridge/intel/sandybridge
device cpu_cluster 0 on
chip cpu/intel/model_206ax
register "acpi_c1" = "1"
register "acpi_c2" = "3"
register "acpi_c3" = "5"
device lapic 0 on end
device lapic 0xacac off end
end
end
device domain 0 on device domain 0 on
device pci 00.0 on end # Host bridge chip southbridge/intel/bd82x6x
device pci 01.0 on end # PCIe bridge for discrete graphics (PCIEX16_1)
device pci 02.0 on end # Internal graphics VGA controller
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "gen1_dec" = "0x000c0291" # HWM register "gen1_dec" = "0x000c0291" # HWM
register "sata_port_map" = "0x33"
register "spi_lvscc" = "0x2005"
register "spi_uvscc" = "0x2005"
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT
device pci 19.0 off end # Intel Gigabit Ethernet
device pci 1a.0 on end # USB2 EHCI #2
device pci 1b.0 on end # High Definition Audio Audio controller
device pci 1c.0 on end # PCIe x1 Port (PCIEX1_1) device pci 1c.0 on end # PCIe x1 Port (PCIEX1_1)
device pci 1c.1 on end # PCIe x1 Port (PCIEX1_2) device pci 1c.1 on end # PCIe x1 Port (PCIEX1_2)
device pci 1c.2 on # Realtek RTL8111E Ethernet Controller device pci 1c.2 on # Realtek RTL8111E Ethernet Controller
@ -43,8 +19,7 @@ chip northbridge/intel/sandybridge
device pci 1c.5 on end # ASMedia ASM1062 SATA Controller device pci 1c.5 on end # ASMedia ASM1062 SATA Controller
device pci 1c.6 off end # Unused PCIe Port device pci 1c.6 off end # Unused PCIe Port
device pci 1c.7 off end # Unused PCIe Port device pci 1c.7 off end # Unused PCIe Port
device pci 1d.0 on end # USB2 EHCI #1
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on # LPC bridge device pci 1f.0 on # LPC bridge
chip superio/nuvoton/nct6776 chip superio/nuvoton/nct6776
device pnp 2e.0 off end # Floppy device pnp 2e.0 off end # Floppy
@ -101,10 +76,6 @@ chip northbridge/intel/sandybridge
device pnp 4e.0 on end # TPM device pnp 4e.0 on end # TPM
end end
end end
device pci 1f.2 on end # SATA Controller 1
device pci 1f.3 on end # SMBus
device pci 1f.5 off end # SATA Controller 2
device pci 1f.6 off end # Thermal
end end
end end
end end