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soc/amd/picasso: Fix the PSP SMI trigger info 

Align coreboot's PSP MboxBiosCmdSmmInfo setup to how AGESA's PSP
library was implemented.  The trigger address must be an SMI trigger
register.  Assign one of the reserved triggers to the PSP.

The #define of SMITYPE_PSP 33 is still correct and is intentionally
unmodified.

This patch should be innocuous as the system doesn't currently support
SMI-based features of the PSP.  The call only exists so the PSP will
honor a mailbox command during S3 suspend.

BUG=b:171815390
TEST=Run SST on Morphius
BRANCH=Zork

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I74029271a522a4f23e54fd76f99a8e3eb0dd4d55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46854
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Marshall Dawson 2020-10-27 16:32:11 -06:00 committed by Felix Held
parent c5e28abaf8
commit 902518e983
2 changed files with 4 additions and 3 deletions
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1
src/soc/amd/picasso/include/soc/smi.h
View File

@ -160,6 +160,7 @@
#define SMI_TIMER_EN (1 << 15)
#define SMI_REG_SMITRIG0 0x98
# define SMITRIG0_PSP (1 << 25)
# define SMITRG0_EOS (1 << 28)
# define SMI_TIMER_SEL (1 << 29)
# define SMITRG0_SMIENB (1 << 31)

6
src/soc/amd/picasso/psp.c
View File

@ -27,11 +27,11 @@ void soc_fill_smm_trig_info(struct smm_trigger_info *trig)
if (!trig)
return;
trig->address = (uintptr_t)acpimmio_smi + SMI_REG_CONTROL2;
trig->address = (uintptr_t)acpimmio_smi + SMI_REG_SMITRIG0;
trig->address_type = SMM_TRIGGER_MEM;
trig->value_width = SMM_TRIGGER_DWORD;
trig->value_and_mask = 0xfdffffff;
trig->value_or_mask = 0x02000000;
trig->value_and_mask = ~SMITRIG0_PSP;
trig->value_or_mask = SMITRIG0_PSP;
}
void soc_fill_smm_reg_info(struct smm_register_info *reg)