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libpayload: Fill gaps in the xHCI driver 

Well, it turned out to be more as some gaps ;)
but we finally have xHCI running. It's well tested against a QM77 Ivy
Bridge board.

We have no SuperSpeed support (yet). On Ivy Bridge, SuperSpeed is not
advertised and USB 3 devices will just work at HighSpeed.

There are still some bit fields in xhci_private.h, so this might need
little more work to run on ARM.

Change-Id: I7a2cb3f226d24573659142565db38b13acdc218c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/3452
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Nico Huber 2013-06-13 14:37:15 +02:00 committed by Stefan Reinauer
parent 5736fab4be
commit 9029265cf5
9 changed files with 2286 additions and 410 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
payloads/libpayload/Config.in
View File

@ -380,8 +380,8 @@ config USB_MSC
config USB_GEN_HUB
bool
default n if (!USB_HUB)
default y if (USB_HUB)
default n if (!USB_HUB && !USB_XHCI)
default y if (USB_HUB || USB_XHCI)
endmenu

4
payloads/libpayload/drivers/Makefile.inc
View File

@ -73,6 +73,10 @@ libc-$(CONFIG_USB_OHCI) += usb/ohci_rh.c
libc-$(CONFIG_USB_EHCI) += usb/ehci.c
libc-$(CONFIG_USB_EHCI) += usb/ehci_rh.c
libc-$(CONFIG_USB_XHCI) += usb/xhci.c
libc-$(CONFIG_USB_XHCI) += usb/xhci_debug.c
libc-$(CONFIG_USB_XHCI) += usb/xhci_devconf.c
libc-$(CONFIG_USB_XHCI) += usb/xhci_events.c
libc-$(CONFIG_USB_XHCI) += usb/xhci_commands.c
libc-$(CONFIG_USB_XHCI) += usb/xhci_rh.c
libc-$(CONFIG_USB_HID) += usb/usbhid.c
libc-$(CONFIG_USB_MSC) += usb/usbmsc.c

947
payloads/libpayload/drivers/usb/xhci.c
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File diff suppressed because it is too large Load Diff

204
payloads/libpayload/drivers/usb/xhci_commands.c Normal file
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@ -0,0 +1,204 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2013 secunet Security Networks AG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <inttypes.h>
#include <arch/virtual.h>
#include "xhci_private.h"
trb_t *
xhci_next_command_trb(xhci_t *const xhci)
{
xhci_clear_trb(xhci->cr.cur, xhci->cr.pcs);
return xhci->cr.cur;
}
void
xhci_post_command(xhci_t *const xhci)
{
xhci_debug("Command %d (@%p)\n",
TRB_GET(TT, xhci->cr.cur), xhci->cr.cur);
TRB_SET(C, xhci->cr.cur, xhci->cr.pcs);
++xhci->cr.cur;
/* Ring the doorbell */
xhci->dbreg[0] = 0;
while (TRB_GET(TT, xhci->cr.cur) == TRB_LINK) {
xhci_debug("Handling LINK pointer (@%p)\n", xhci->cr.cur);
const int tc = TRB_GET(TC, xhci->cr.cur);
TRB_SET(C, xhci->cr.cur, xhci->cr.pcs);
xhci->cr.cur = phys_to_virt(xhci->cr.cur->ptr_low);
if (tc)
xhci->cr.pcs ^= 1;
}
}
static int
xhci_wait_for_command(xhci_t *const xhci,
const trb_t *const cmd_trb,
const int clear_event)
{
int cc;
cc = xhci_wait_for_command_done(xhci, cmd_trb, clear_event);
if (cc != TIMEOUT)
return cc;
/* Abort command on timeout */
xhci_debug("Aborting command (@%p), CRCR: 0x%"PRIx32"\n",
cmd_trb, xhci->opreg->crcr_lo);
xhci->opreg->crcr_lo |= CRCR_CS | CRCR_CA;
xhci->opreg->crcr_hi = 0;
cc = xhci_wait_for_command_aborted(xhci, cmd_trb);
if (xhci->opreg->crcr_lo & CRCR_CRR)
fatal("xhci_wait_for_command: Command ring still running\n");
return cc;
}
/*
* xhci_cmd_* return >= 0: xhci completion code (cc)
* < 0: driver error code
*/
int
xhci_cmd_enable_slot(xhci_t *const xhci, int *const slot_id)
{
trb_t *const cmd = xhci_next_command_trb(xhci);
TRB_SET(TT, cmd, TRB_CMD_ENABLE_SLOT);
xhci_post_command(xhci);
int cc = xhci_wait_for_command(xhci, cmd, 0);
if (cc >= 0) {
if (cc == CC_SUCCESS) {
*slot_id = TRB_GET(ID, xhci->er.cur);
if (*slot_id > xhci->max_slots_en)
cc = CONTROLLER_ERROR;
}
xhci_advance_event_ring(xhci);
xhci_handle_events(xhci);
}
return cc;
}
int
xhci_cmd_disable_slot(xhci_t *const xhci, const int slot_id)
{
trb_t *const cmd = xhci_next_command_trb(xhci);
TRB_SET(TT, cmd, TRB_CMD_DISABLE_SLOT);
TRB_SET(ID, cmd, slot_id);
xhci_post_command(xhci);
return xhci_wait_for_command(xhci, cmd, 1);
}
int
xhci_cmd_address_device(xhci_t *const xhci,
const int slot_id,
inputctx_t *const ic)
{
trb_t *const cmd = xhci_next_command_trb(xhci);
TRB_SET(TT, cmd, TRB_CMD_ADDRESS_DEV);
TRB_SET(ID, cmd, slot_id);
cmd->ptr_low = virt_to_phys(ic);
xhci_post_command(xhci);
return xhci_wait_for_command(xhci, cmd, 1);
}
int
xhci_cmd_configure_endpoint(xhci_t *const xhci,
const int slot_id,
const int config_id,
inputctx_t *const ic)
{
trb_t *const cmd = xhci_next_command_trb(xhci);
TRB_SET(TT, cmd, TRB_CMD_CONFIGURE_EP);
TRB_SET(ID, cmd, slot_id);
cmd->ptr_low = virt_to_phys(ic);
if (config_id == 0)
TRB_SET(DC, cmd, 1);
xhci_post_command(xhci);
return xhci_wait_for_command(xhci, cmd, 1);
}
int
xhci_cmd_evaluate_context(xhci_t *const xhci,
const int slot_id,
inputctx_t *const ic)
{
trb_t *const cmd = xhci_next_command_trb(xhci);
TRB_SET(TT, cmd, TRB_CMD_EVAL_CTX);
TRB_SET(ID, cmd, slot_id);
cmd->ptr_low = virt_to_phys(ic);
xhci_post_command(xhci);
return xhci_wait_for_command(xhci, cmd, 1);
}
int
xhci_cmd_reset_endpoint(xhci_t *const xhci, const int slot_id, const int ep)
{
trb_t *const cmd = xhci_next_command_trb(xhci);
TRB_SET(TT, cmd, TRB_CMD_RESET_EP);
TRB_SET(ID, cmd, slot_id);
TRB_SET(EP, cmd, ep);
xhci_post_command(xhci);
return xhci_wait_for_command(xhci, cmd, 1);
}
int
xhci_cmd_stop_endpoint(xhci_t *const xhci, const int slot_id, const int ep)
{
trb_t *const cmd = xhci_next_command_trb(xhci);
TRB_SET(TT, cmd, TRB_CMD_STOP_EP);
TRB_SET(ID, cmd, slot_id);
TRB_SET(EP, cmd, ep);
xhci_post_command(xhci);
return xhci_wait_for_command(xhci, cmd, 1);
}
int
xhci_cmd_set_tr_dq(xhci_t *const xhci, const int slot_id, const int ep,
trb_t *const dq_trb, const int dcs)
{
trb_t *const cmd = xhci_next_command_trb(xhci);
TRB_SET(TT, cmd, TRB_CMD_SET_TR_DQ);
TRB_SET(ID, cmd, slot_id);
TRB_SET(EP, cmd, ep);
cmd->ptr_low = virt_to_phys(dq_trb) | dcs;
xhci_post_command(xhci);
return xhci_wait_for_command(xhci, cmd, 1);
}

136
payloads/libpayload/drivers/usb/xhci_debug.c Normal file
View File

@ -0,0 +1,136 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2013 secunet Security Networks AG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <inttypes.h>
#include "xhci_private.h"
#ifdef XHCI_DUMPS
void
xhci_dump_slotctx(const slotctx_t *const sc)
{
xhci_debug("Slot Context (@%p):\n", sc);
usb_debug(" FIELD1\t0x%08"PRIx32"\n", sc->f1);
usb_debug(" FIELD2\t0x%08"PRIx32"\n", sc->f2);
usb_debug(" FIELD3\t0x%08"PRIx32"\n", sc->f3);
usb_debug(" FIELD4\t0x%08"PRIx32"\n", sc->f4);
SC_DUMP(ROUTE, *sc);
SC_DUMP(SPEED, *sc);
SC_DUMP(MTT, *sc);
SC_DUMP(HUB, *sc);
SC_DUMP(CTXENT, *sc);
SC_DUMP(RHPORT, *sc);
SC_DUMP(NPORTS, *sc);
SC_DUMP(TTID, *sc);
SC_DUMP(TTPORT, *sc);
SC_DUMP(TTT, *sc);
SC_DUMP(UADDR, *sc);
SC_DUMP(STATE, *sc);
}
void
xhci_dump_epctx(const epctx_t *const ec)
{
xhci_debug("Endpoint Context (@%p):\n", ec);
usb_debug(" FIELD1\t0x%08"PRIx32"\n", ec->f1);
usb_debug(" FIELD2\t0x%08"PRIx32"\n", ec->f2);
usb_debug(" TRDQ_L\t0x%08"PRIx32"\n", ec->tr_dq_low);
usb_debug(" TRDQ_H\t0x%08"PRIx32"\n", ec->tr_dq_high);
usb_debug(" FIELD5\t0x%08"PRIx32"\n", ec->f5);
EC_DUMP(STATE, *ec);
EC_DUMP(INTVAL, *ec);
EC_DUMP(CERR, *ec);
EC_DUMP(TYPE, *ec);
EC_DUMP(MBS, *ec);
EC_DUMP(MPS, *ec);
EC_DUMP(DCS, *ec);
EC_DUMP(AVRTRB, *ec);
EC_DUMP(MXESIT, *ec);
}
void
xhci_dump_devctx(const devctx_t *const dc, const u32 ctx_mask)
{
int i;
if (ctx_mask & 1)
xhci_dump_slotctx(&dc->slot);
for (i = 0; i < SC_GET(CTXENT, dc->slot); ++i) {
if (ctx_mask & (2 << i))
xhci_dump_epctx(&dc->all_eps[i]);
}
}
void
xhci_dump_inputctx(const inputctx_t *const ic)
{
xhci_debug("Input Control add: 0x%08"PRIx32"\n", ic->control.add);
xhci_debug("Input Control drop: 0x%08"PRIx32"\n", ic->control.drop);
xhci_dump_devctx(&ic->dev, ic->control.add);
}
void
xhci_dump_transfer_trb(const trb_t *const cur)
{
xhci_debug("Transfer TRB (@%p):\n", cur);
usb_debug(" PTR_L\t0x%08"PRIx32"\n", cur->ptr_low);
usb_debug(" PTR_H\t0x%08"PRIx32"\n", cur->ptr_high);
usb_debug(" STATUS\t0x%08"PRIx32"\n", cur->status);
usb_debug(" CNTRL\t0x%08"PRIx32"\n", cur->control);
TRB_DUMP(TL, cur);
TRB_DUMP(TDS, cur);
TRB_DUMP(C, cur);
TRB_DUMP(ISP, cur);
TRB_DUMP(CH, cur);
TRB_DUMP(IOC, cur);
TRB_DUMP(IDT, cur);
TRB_DUMP(TT, cur);
TRB_DUMP(DIR, cur);
}
static const trb_t *
xhci_next_trb(const trb_t *const cur)
{
if (TRB_GET(TT, cur) == TRB_LINK)
return (!cur->ptr_low) ? NULL : phys_to_virt(cur->ptr_low);
else
return cur + 1;
}
void
xhci_dump_transfer_trbs(const trb_t *const first, const trb_t *const last)
{
const trb_t *cur;
for (cur = first; cur; cur = xhci_next_trb(cur)) {
xhci_dump_transfer_trb(cur);
if (cur == last)
break;
}
}
#endif

425
payloads/libpayload/drivers/usb/xhci_devconf.c Normal file
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@ -0,0 +1,425 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2013 secunet Security Networks AG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
//#define XHCI_SPEW_DEBUG
#include <arch/virtual.h>
#include "xhci_private.h"
static u32
xhci_gen_route(xhci_t *const xhci, const int hubport, const int hubaddr)
{
if (!hubaddr)
return 0;
volatile const devctx_t *const devctx =
phys_to_virt(xhci->dcbaa[hubaddr]);
u32 route_string = SC_GET(ROUTE, devctx->slot);
int i;
for (i = 0; i < 20; i += 4) {
if (!(route_string & (0xf << i))) {
route_string |= (hubport & 0xf) << i;
break;
}
}
return route_string;
}
static int
xhci_get_rh_port(xhci_t *const xhci, const int hubport, const int hubaddr)
{
if (!hubaddr)
return hubport;
volatile const devctx_t *const devctx =
phys_to_virt(xhci->dcbaa[hubaddr]);
return SC_GET(RHPORT, devctx->slot);
}
static int
xhci_get_tt(xhci_t *const xhci, const int xhci_speed,
const int hubport, const int hubaddr,
int *const tt, int *const tt_port)
{
if (!hubaddr)
return 0;
volatile const devctx_t *const devctx =
phys_to_virt(xhci->dcbaa[hubaddr]);
if ((*tt = SC_GET(TTID, devctx->slot))) {
*tt_port = SC_GET(TTPORT, devctx->slot);
} else if (xhci_speed < XHCI_HIGH_SPEED &&
SC_GET(SPEED, devctx->slot) == XHCI_HIGH_SPEED) {
*tt = hubaddr;
*tt_port = hubport;
}
return *tt != 0;
}
static long
xhci_decode_mps0(const int xhci_speed, const u8 b_mps)
{
switch (xhci_speed) {
case XHCI_LOW_SPEED:
case XHCI_FULL_SPEED:
case XHCI_HIGH_SPEED:
switch (b_mps) {
case 8: case 16: case 32: case 64:
return b_mps;
default:
xhci_debug("Invalid MPS0: 0x%02x\n", b_mps);
return 8;
}
break;
case XHCI_SUPER_SPEED:
if (b_mps == 9) {
return 2 << b_mps;
} else {
xhci_debug("Invalid MPS0: 0x%02x\n", b_mps);
return 2 << 9;
}
break;
default:
xhci_debug("Invalid speed for MPS0: %d\n", xhci_speed);
return 8;
}
}
static long
xhci_get_mps0(usbdev_t *const dev, const int xhci_speed)
{
u8 buf[8];
dev_req_t dr = {
.bmRequestType = gen_bmRequestType(
device_to_host, standard_type, dev_recp),
.data_dir = device_to_host,
.bRequest = GET_DESCRIPTOR,
.wValue = (1 << 8),
.wIndex = 0,
.wLength = 8,
};
if (dev->controller->control(dev, IN, sizeof(dr), &dr, 8, buf)) {
xhci_debug("Failed to read MPS0\n");
return COMMUNICATION_ERROR;
} else {
return xhci_decode_mps0(xhci_speed, buf[7]);
}
}
int
xhci_set_address (hci_t *controller, int speed, int hubport, int hubaddr)
{
xhci_t *const xhci = XHCI_INST(controller);
const int xhci_speed = speed + 1;
int ret = -1;
inputctx_t *const ic = xhci_align(64, sizeof(*ic));
devinfo_t *const di = memalign(sizeof(di->devctx), sizeof(*di));
transfer_ring_t *const tr = malloc(sizeof(*tr));
if (tr)
tr->ring = xhci_align(16, TRANSFER_RING_SIZE * sizeof(trb_t));
if (!ic || !di || !tr || !tr->ring) {
xhci_debug("Out of memory\n");
goto _free_return;
}
int slot_id;
int cc = xhci_cmd_enable_slot(xhci, &slot_id);
if (cc != CC_SUCCESS) {
xhci_debug("Enable slot failed: %d\n", cc);
goto _free_return;
} else {
xhci_debug("Enabled slot %d\n", slot_id);
}
memset(ic, 0x00, sizeof(*ic));
ic->control.add = (1 << 0) /* Slot Context */ |
(1 << 1) /* EP0 Context */ ;
SC_SET(ROUTE, ic->dev.slot, xhci_gen_route(xhci, hubport, hubaddr));
SC_SET(SPEED, ic->dev.slot, xhci_speed);
SC_SET(CTXENT, ic->dev.slot, 1); /* the endpoint 0 context */
SC_SET(RHPORT, ic->dev.slot, xhci_get_rh_port(xhci, hubport, hubaddr));
int tt, tt_port;
if (xhci_get_tt(xhci, xhci_speed, hubport, hubaddr, &tt, &tt_port)) {
xhci_debug("TT for %d: %d[%d]\n", slot_id, tt, tt_port);
volatile const devctx_t *const ttctx =
phys_to_virt(xhci->dcbaa[tt]);
SC_SET(MTT, ic->dev.slot, SC_GET(MTT, ttctx->slot));
SC_SET(TTID, ic->dev.slot, tt);
SC_SET(TTPORT, ic->dev.slot, tt_port);
}
memset(di, 0x00, sizeof(*di));
di->transfer_rings[1] = tr;
xhci_init_cycle_ring(tr, TRANSFER_RING_SIZE);
ic->dev.ep0.tr_dq_low = virt_to_phys(tr->ring);
ic->dev.ep0.tr_dq_high = 0;
EC_SET(TYPE, ic->dev.ep0, EP_CONTROL);
EC_SET(AVRTRB, ic->dev.ep0, 8);
EC_SET(MPS, ic->dev.ep0, 8);
EC_SET(CERR, ic->dev.ep0, 3);
EC_SET(DCS, ic->dev.ep0, 1);
volatile devctx_t *const oc = &di->devctx;
xhci->dcbaa[slot_id] = virt_to_phys(oc);
cc = xhci_cmd_address_device(xhci, slot_id, ic);
if (cc != CC_SUCCESS) {
xhci_debug("Address device failed: %d\n", cc);
goto _disable_return;
} else {
xhci_debug("Addressed device %d (USB: %d)\n",
slot_id, SC_GET(UADDR, oc->slot));
}
mdelay(2); /* SetAddress() recovery interval (usb20 spec 9.2.6.3) */
init_device_entry(controller, slot_id);
controller->devices[slot_id]->address = slot_id;
const long mps0 = xhci_get_mps0(
controller->devices[slot_id], xhci_speed);
if (mps0 < 0) {
goto _disable_return;
} else if (mps0 != 8) {
memset(&ic->control, 0x00, sizeof(ic->control));
memset(&ic->dev.ep0, 0x00, sizeof(ic->dev.ep0));
ic->control.add = (1 << 1); /* EP0 Context */
EC_SET(MPS, ic->dev.ep0, mps0);
cc = xhci_cmd_evaluate_context(xhci, slot_id, ic);
if (cc != CC_SUCCESS) {
xhci_debug("Context evaluation failed: %d\n", cc);
goto _disable_return;
} else {
xhci_debug("Set MPS0 to %dB\n", mps0);
}
}
ret = slot_id;
goto _free_ic_return;
_disable_return:
xhci_cmd_disable_slot(xhci, slot_id);
xhci->dcbaa[slot_id] = 0;
_free_return:
if (tr)
free((void *)tr->ring);
free(tr);
free((void *)di);
_free_ic_return:
free(ic);
return ret;
}
static int
xhci_finish_hub_config(usbdev_t *const dev, inputctx_t *const ic)
{
hub_descriptor_t *const descriptor = (hub_descriptor_t *)
get_descriptor(
dev,
gen_bmRequestType(device_to_host, class_type, dev_recp),
0x29, 0, 0);
if (!descriptor) {
xhci_debug("Failed to fetch hub descriptor\n");
return COMMUNICATION_ERROR;
}
SC_SET(HUB, ic->dev.slot, 1);
SC_SET(MTT, ic->dev.slot, 0); /* No support for Multi-TT */
SC_SET(NPORTS, ic->dev.slot, descriptor->bNbrPorts);
if (dev->speed == HIGH_SPEED)
SC_SET(TTT, ic->dev.slot,
(descriptor->wHubCharacteristics >> 5) & 0x0003);
free(descriptor);
return 0;
}
static size_t
xhci_bound_interval(const endpoint_t *const ep)
{
if ( (ep->dev->speed == LOW_SPEED &&
(ep->type == ISOCHRONOUS ||
ep->type == INTERRUPT)) ||
(ep->dev->speed == FULL_SPEED &&
ep->type == INTERRUPT))
{
if (ep->interval < 3)
return 3;
else if (ep->interval > 11)
return 11;
else
return ep->interval;
} else {
if (ep->interval < 0)
return 0;
else if (ep->interval > 15)
return 15;
else
return ep->interval;
}
}
static int
xhci_finish_ep_config(const endpoint_t *const ep, inputctx_t *const ic)
{
xhci_t *const xhci = XHCI_INST(ep->dev->controller);
devinfo_t *const di = phys_to_virt(xhci->dcbaa[ep->dev->address]
- offsetof(devinfo_t, devctx));
const int ep_id = xhci_ep_id(ep);
xhci_debug("ep_id: %d\n", ep_id);
if (ep_id <= 1 || 32 <= ep_id)
return DRIVER_ERROR;
transfer_ring_t *const tr = malloc(sizeof(*tr));
if (tr)
tr->ring = xhci_align(16, TRANSFER_RING_SIZE * sizeof(trb_t));
if (!tr || !tr->ring) {
free(tr);
xhci_debug("Out of memory\n");
return OUT_OF_MEMORY;
}
di->transfer_rings[ep_id] = tr;
xhci_init_cycle_ring(tr, TRANSFER_RING_SIZE);
ic->control.add |= (1 << ep_id);
if (SC_GET(CTXENT, ic->dev.slot) < ep_id)
SC_SET(CTXENT, ic->dev.slot, ep_id);
epctx_t *const epctx = &ic->dev.eps[ep_id];
xhci_debug("Filling epctx (@%p)\n", epctx);
epctx->tr_dq_low = virt_to_phys(tr->ring);
epctx->tr_dq_high = 0;
EC_SET(INTVAL, *epctx, xhci_bound_interval(ep));
EC_SET(CERR, *epctx, 3);
EC_SET(TYPE, *epctx, ep->type | ((ep->direction != OUT) << 2));
EC_SET(MPS, *epctx, ep->maxpacketsize);
EC_SET(DCS, *epctx, 1);
size_t avrtrb;
switch (ep->type) {
case BULK: case ISOCHRONOUS: avrtrb = 3 * 1024; break;
case INTERRUPT: avrtrb = 1024; break;
default: avrtrb = 8; break;
}
EC_SET(AVRTRB, *epctx, avrtrb);
EC_SET(MXESIT, *epctx, EC_GET(MPS, *epctx) * EC_GET(MBS, *epctx));
return 0;
}
int
xhci_finish_device_config(usbdev_t *const dev)
{
xhci_t *const xhci = XHCI_INST(dev->controller);
devinfo_t *const di = phys_to_virt(xhci->dcbaa[dev->address]
- offsetof(devinfo_t, devctx));
int i, ret = 0;
inputctx_t *const ic = xhci_align(64, sizeof(*ic));
if (!ic) {
xhci_debug("Out of memory\n");
return OUT_OF_MEMORY;
}
memset(ic, 0x00, sizeof(*ic));
ic->control.add = (1 << 0); /* Slot Context */
xhci_dump_slotctx((const slotctx_t *)&di->devctx.slot);
ic->dev.slot.f1 = di->devctx.slot.f1;
ic->dev.slot.f2 = di->devctx.slot.f2;
ic->dev.slot.f3 = di->devctx.slot.f3;
if (((device_descriptor_t *)dev->descriptor)->bDeviceClass == 0x09) {
ret = xhci_finish_hub_config(dev, ic);
if (ret)
goto _free_return;
}
for (i = 1; i < dev->num_endp; ++i) {
ret = xhci_finish_ep_config(&dev->endpoints[i], ic);
if (ret)
goto _free_ep_ctx_return;
}
xhci_dump_inputctx(ic);
const int config_id = ((configuration_descriptor_t *)
dev->configuration)->bConfigurationValue;
xhci_debug("config_id: %d\n", config_id);
const int cc =
xhci_cmd_configure_endpoint(xhci, dev->address, config_id, ic);
if (cc != CC_SUCCESS) {
xhci_debug("Configure endpoint failed: %d\n", cc);
ret = CONTROLLER_ERROR;
goto _free_ep_ctx_return;
} else {
xhci_debug("Endpoints configured\n");
}
goto _free_return;
_free_ep_ctx_return:
for (i = 2; i < 31; ++i) {
if (di->transfer_rings[i])
free((void *)di->transfer_rings[i]->ring);
free(di->transfer_rings[i]);
di->transfer_rings[i] = NULL;
}
_free_return:
free(ic);
return ret;
}
void
xhci_destroy_dev(hci_t *const controller, const int slot_id)
{
xhci_t *const xhci = XHCI_INST(controller);
if (slot_id <= 0 || xhci->max_slots_en > slot_id)
return;
int i;
const int cc = xhci_cmd_disable_slot(xhci, slot_id);
if (cc != CC_SUCCESS)
xhci_debug("Failed to disable slot %d: %d\n", slot_id, cc);
devinfo_t *const di = DEVINFO_FROM_XHCI(xhci, slot_id);
for (i = 1; i < 31; ++i) {
if (di->transfer_rings[i])
free((void *)di->transfer_rings[i]->ring);
free(di->transfer_rings[i]);
free(di->interrupt_queues[i]);
}
free(di);
xhci->dcbaa[slot_id] = 0;
}

333
payloads/libpayload/drivers/usb/xhci_events.c Normal file
View File

@ -0,0 +1,333 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2013 secunet Security Networks AG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
//#define XHCI_SPEW_DEBUG
#include <inttypes.h>
#include <arch/virtual.h>
#include "xhci_private.h"
void
xhci_reset_event_ring(event_ring_t *const er)
{
int i;
for (i = 0; i < EVENT_RING_SIZE; ++i)
er->ring[i].control &= ~TRB_CYCLE;
er->cur = er->ring;
er->last = er->ring + EVENT_RING_SIZE;
er->ccs = 1;
er->adv = 1;
}
static inline int
xhci_event_ready(const event_ring_t *const er)
{
return (er->cur->control & TRB_CYCLE) == er->ccs;
}
void
xhci_update_event_dq(xhci_t *const xhci)
{
if (xhci->er.adv) {
xhci_spew("Updating dq ptr: @%p(0x%08"PRIx32") -> %p\n",
phys_to_virt(xhci->hcrreg->intrrs[0].erdp_lo),
xhci->hcrreg->intrrs[0].erdp_lo, xhci->er.cur);
xhci->hcrreg->intrrs[0].erdp_lo = virt_to_phys(xhci->er.cur);
xhci->hcrreg->intrrs[0].erdp_hi = 0;
xhci->er.adv = 0;
}
}
void
xhci_advance_event_ring(xhci_t *const xhci)
{
xhci->er.cur++;
xhci->er.adv = 1;
if (xhci->er.cur == xhci->er.last) {
xhci_spew("Roll over in event ring\n");
xhci->er.cur = xhci->er.ring;
xhci->er.ccs ^= 1;
xhci_update_event_dq(xhci);
}
}
static void
xhci_handle_transfer_event(xhci_t *const xhci)
{
const trb_t *const ev = xhci->er.cur;
const int cc = TRB_GET(CC, ev);
const int id = TRB_GET(ID, ev);
const int ep = TRB_GET(EP, ev);
devinfo_t *di;
intrq_t *intrq;
if (id && id <= xhci->max_slots_en &&
(di = DEVINFO_FROM_XHCI(xhci, id)) &&
(intrq = di->interrupt_queues[ep])) {
/* It's a running interrupt endpoint */
intrq->ready = phys_to_virt(ev->ptr_low);
if (cc == CC_SUCCESS || cc == CC_SHORT_PACKET) {
TRB_SET(TL, intrq->ready,
intrq->size - TRB_GET(EVTL, ev));
} else {
xhci_debug("Interrupt Transfer failed: %d\n",
cc);
TRB_SET(TL, intrq->ready, 0);
}
} else if (cc == CC_STOPPED || cc == CC_STOPPED_LENGTH_INVALID) {
/* Ignore 'Forced Stop Events' */
} else {
xhci_debug("Warning: "
"Spurious transfer event for ID %d, EP %d:\n"
" Pointer: 0x%08x%08x\n"
" TL: 0x%06x\n"
" CC: %d\n",
id, ep,
ev->ptr_high, ev->ptr_low,
TRB_GET(EVTL, ev), cc);
}
xhci_advance_event_ring(xhci);
}
static void
xhci_handle_command_completion_event(xhci_t *const xhci)
{
const trb_t *const ev = xhci->er.cur;
xhci_debug("Warning: Spurious command completion event:\n"
" Pointer: 0x%08x%08x\n"
" CC: %d\n"
" Slot ID: %d\n"
" Cycle: %d\n",
ev->ptr_high, ev->ptr_low,
TRB_GET(CC, ev), TRB_GET(ID, ev), ev->control & TRB_CYCLE);
xhci_advance_event_ring(xhci);
}
static void
xhci_handle_host_controller_event(xhci_t *const xhci)
{
const trb_t *const ev = xhci->er.cur;
const int cc = TRB_GET(CC, ev);
switch (cc) {
case CC_EVENT_RING_FULL_ERROR:
xhci_debug("Event ring full! (@%p)\n", xhci->er.cur);
/*
* If we get here, we have processed the whole queue:
* xHC pushes this event, when it sees the ring full,
* full of other events.
* IMO it's save and necessary to update the dequeue
* pointer here.
*/
xhci_advance_event_ring(xhci);
xhci_update_event_dq(xhci);
break;
default:
xhci_debug("Warning: Spurious host controller event: %d\n", cc);
xhci_advance_event_ring(xhci);
break;
}
}
/* handle standard types:
* - command completion event
* - port status change event
* - transfer event
* - host controller event
*/
static void
xhci_handle_event(xhci_t *const xhci)
{
const trb_t *const ev = xhci->er.cur;
const int trb_type = TRB_GET(TT, ev);
switch (trb_type) {
/* Either pass along the event or advance event ring */
case TRB_EV_TRANSFER:
xhci_handle_transfer_event(xhci);
break;
case TRB_EV_CMD_CMPL:
xhci_handle_command_completion_event(xhci);
break;
case TRB_EV_PORTSC:
xhci_debug("Port Status Change Event for %d: %d\n",
TRB_GET(PORT, ev), TRB_GET(CC, ev));
/* We ignore the event as we look for the PORTSC
registers instead, at a time when it suits _us_. */
xhci_advance_event_ring(xhci);
break;
case TRB_EV_HOST:
xhci_handle_host_controller_event(xhci);
break;
default:
xhci_debug("Warning: Spurious event: %d, Completion Code: %d\n",
trb_type, TRB_GET(CC, ev));
xhci_advance_event_ring(xhci);
break;
}
}
void
xhci_handle_events(xhci_t *const xhci)
{
while (xhci_event_ready(&xhci->er))
xhci_handle_event(xhci);
xhci_update_event_dq(xhci);
}
static unsigned long
xhci_wait_for_event(const event_ring_t *const er,
unsigned long *const timeout_us)
{
while (!xhci_event_ready(er) && *timeout_us) {
--*timeout_us;
udelay(1);
}
return *timeout_us;
}
static unsigned long
xhci_wait_for_event_type(xhci_t *const xhci,
const int trb_type,
unsigned long *const timeout_us)
{
while (xhci_wait_for_event(&xhci->er, timeout_us)) {
if (TRB_GET(TT, xhci->er.cur) == trb_type)
break;
xhci_handle_event(xhci);
}
return *timeout_us;
}
/* returns cc of command in question (pointed to by `address`) */
int
xhci_wait_for_command_aborted(xhci_t *const xhci, const trb_t *const address)
{
/*
* Specification says that something might be seriously wrong, if
* we don't get a response after 5s. Still, let the caller decide,
* what to do then.
*/
unsigned long timeout_us = 5 * 1000 * 1000; /* 5s */
int cc = TIMEOUT;
/*
* Expects two command completion events:
* The first with CC == COMMAND_ABORTED should point to address,
* the second with CC == COMMAND_RING_STOPPED should point to new dq.
*/
while (xhci_wait_for_event_type(xhci, TRB_EV_CMD_CMPL, &timeout_us)) {
if ((xhci->er.cur->ptr_low == virt_to_phys(address)) &&
(xhci->er.cur->ptr_high == 0)) {
cc = TRB_GET(CC, xhci->er.cur);
xhci_advance_event_ring(xhci);
break;
}
xhci_handle_command_completion_event(xhci);
}
if (!timeout_us)
xhci_debug("Warning: Timed out waiting for COMMAND_ABORTED.\n");
while (xhci_wait_for_event_type(xhci, TRB_EV_CMD_CMPL, &timeout_us)) {
if (TRB_GET(CC, xhci->er.cur) == CC_COMMAND_RING_STOPPED) {
xhci->cr.cur = phys_to_virt(xhci->er.cur->ptr_low);
xhci_advance_event_ring(xhci);
break;
}
xhci_handle_command_completion_event(xhci);
}
if (!timeout_us)
xhci_debug("Warning: Timed out "
"waiting for COMMAND_RING_STOPPED.\n");
xhci_update_event_dq(xhci);
return cc;
}
/*
* returns cc of command in question (pointed to by `address`)
* caller should abort command if cc is TIMEOUT
*/
int
xhci_wait_for_command_done(xhci_t *const xhci,
const trb_t *const address,
const int clear_event)
{
/*
* The Address Device Command should take most time, as it has to
* communicate with the USB device. Set address processing shouldn't
* take longer than 50ms (at the slave). Let's take a timeout of
* 100ms.
*/
unsigned long timeout_us = 100 * 1000; /* 100ms */
int cc = TIMEOUT;
while (xhci_wait_for_event_type(xhci, TRB_EV_CMD_CMPL, &timeout_us)) {
if ((xhci->er.cur->ptr_low == virt_to_phys(address)) &&
(xhci->er.cur->ptr_high == 0)) {
cc = TRB_GET(CC, xhci->er.cur);
break;
}
xhci_handle_command_completion_event(xhci);
}
if (!timeout_us) {
xhci_debug("Warning: Timed out waiting for TRB_EV_CMD_CMPL.\n");
} else if (clear_event) {
xhci_advance_event_ring(xhci);
}
xhci_update_event_dq(xhci);
return cc;
}
/* returns cc of transfer for given slot/endpoint pair */
int
xhci_wait_for_transfer(xhci_t *const xhci, const int slot_id, const int ep_id)
{
xhci_spew("Waiting for transfer on ID %d EP %d\n", slot_id, ep_id);
/* 2s for all types of transfers */ /* TODO: test, wait longer? */
unsigned long timeout_us = 2 * 1000 * 1000;
int cc = TIMEOUT;
while (xhci_wait_for_event_type(xhci, TRB_EV_TRANSFER, &timeout_us)) {
if (TRB_GET(ID, xhci->er.cur) == slot_id &&
TRB_GET(EP, xhci->er.cur) == ep_id) {
cc = TRB_GET(CC, xhci->er.cur);
xhci_advance_event_ring(xhci);
break;
}
xhci_handle_transfer_event(xhci);
}
if (!timeout_us)
xhci_debug("Warning: Timed out waiting for TRB_EV_TRANSFER.\n");
xhci_update_event_dq(xhci);
return cc;
}

483
payloads/libpayload/drivers/usb/xhci_private.h
View File

@ -2,6 +2,7 @@
* This file is part of the libpayload project.
*
* Copyright (C) 2010 Patrick Georgi
* Copyright (C) 2013 secunet Security Networks AG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -30,159 +31,268 @@
#ifndef __XHCI_PRIVATE_H
#define __XHCI_PRIVATE_H
//#define USB_DEBUG
#include <usb/usb.h>
//#define XHCI_DUMPS
#define xhci_debug(fmt, args...) usb_debug("%s: " fmt, __func__, ## args)
#ifdef XHCI_SPEW_DEBUG
# define xhci_spew(fmt, args...) xhci_debug(fmt, ##args)
#else
# define xhci_spew(fmt, args...) do {} while(0)
#endif
#define MASK(startbit, lenbit) (((1<<(lenbit))-1)<<(startbit))
typedef volatile union trb {
// transfer
enum { XHCI_FULL_SPEED = 1, XHCI_LOW_SPEED = 2, XHCI_HIGH_SPEED = 3, XHCI_SUPER_SPEED = 4 };
// events
#define TRB_EV_CMD_CMPL 33
struct {
u32 Cmd_TRB_Pointer_lo;
u32 Cmd_TRB_Pointer_hi;
struct {
unsigned long:24;
unsigned long Completion_Code:8;
} __attribute__ ((packed));
struct {
unsigned long C:1;
unsigned long:9;
unsigned long TRB_Type:6;
unsigned long VF_ID:8;
unsigned long Slot_ID:8;
} __attribute__ ((packed));
} __attribute__ ((packed)) event_cmd_cmpl;
#define TIMEOUT -1
#define CONTROLLER_ERROR -2
#define COMMUNICATION_ERROR -3
#define OUT_OF_MEMORY -4
#define DRIVER_ERROR -5
#define TRB_EV_PORTSC 34
struct {
struct {
unsigned long:24;
unsigned long Port:8;
} __attribute__ ((packed));
u32 rsvd;
struct {
unsigned long:24;
unsigned long Completion_Code:8;
} __attribute__ ((packed));
struct {
unsigned long C:1;
unsigned long:9;
unsigned long TRB_Type:6;
unsigned long:16;
} __attribute__ ((packed));
} __attribute__ ((packed)) event_portsc;
#define CC_SUCCESS 1
#define CC_TRB_ERROR 5
#define CC_STALL_ERROR 6
#define CC_SHORT_PACKET 13
#define CC_EVENT_RING_FULL_ERROR 21
#define CC_COMMAND_RING_STOPPED 24
#define CC_COMMAND_ABORTED 25
#define CC_STOPPED 26
#define CC_STOPPED_LENGTH_INVALID 27
// commands
#define TRB_CMD_NOOP 23
struct {
u32 rsvd[3];
struct {
unsigned long C:1;
unsigned long:9;
unsigned long TRB_Type:6;
unsigned long:16;
} __attribute__ ((packed));
} __attribute__ ((packed)) cmd_No_Op;
enum {
TRB_NORMAL = 1,
TRB_SETUP_STAGE = 2, TRB_DATA_STAGE = 3, TRB_STATUS_STAGE = 4,
TRB_LINK = 6,
TRB_CMD_ENABLE_SLOT = 9, TRB_CMD_DISABLE_SLOT = 10, TRB_CMD_ADDRESS_DEV = 11,
TRB_CMD_CONFIGURE_EP = 12, TRB_CMD_EVAL_CTX = 13, TRB_CMD_RESET_EP = 14,
TRB_CMD_STOP_EP = 15, TRB_CMD_SET_TR_DQ = 16, TRB_CMD_NOOP = 23,
TRB_EV_TRANSFER = 32, TRB_EV_CMD_CMPL = 33, TRB_EV_PORTSC = 34, TRB_EV_HOST = 37,
};
enum { TRB_TRT_NO_DATA = 0, TRB_TRT_OUT_DATA = 2, TRB_TRT_IN_DATA = 3 };
enum { TRB_DIR_OUT = 0, TRB_DIR_IN = 1 };
// "others"
struct {
u32 Ring_Segment_Ptr_lo;
u32 Ring_Segment_Ptr_hi;
struct {
unsigned long:22;
unsigned long Interrupter_Target;
} __attribute__ ((packed));
struct {
unsigned long C:1;
unsigned long TC:1;
unsigned long:2;
unsigned long CH:1;
unsigned long IOC:1;
unsigned long:4;
unsigned long TRB_Type:6;
unsigned long:16;
} __attribute__ ((packed));
} __attribute__ ((packed)) link;
#define TRB_PORT_FIELD ptr_low
#define TRB_PORT_START 24
#define TRB_PORT_LEN 8
#define TRB_TL_FIELD status /* TL - Transfer Length */
#define TRB_TL_START 0
#define TRB_TL_LEN 17
#define TRB_EVTL_FIELD status /* EVTL - (Event TRB) Transfer Length */
#define TRB_EVTL_START 0
#define TRB_EVTL_LEN 24
#define TRB_TDS_FIELD status /* TDS - TD Size */
#define TRB_TDS_START 17
#define TRB_TDS_LEN 5
#define TRB_CC_FIELD status /* CC - Completion Code */
#define TRB_CC_START 24
#define TRB_CC_LEN 8
#define TRB_C_FIELD control /* C - Cycle Bit */
#define TRB_C_START 0
#define TRB_C_LEN 1
#define TRB_TC_FIELD control /* TC - Toggle Cycle */
#define TRB_TC_START 1
#define TRB_TC_LEN 1
#define TRB_ISP_FIELD control /* ISP - Interrupt-on Short Packet */
#define TRB_ISP_START 2
#define TRB_ISP_LEN 1
#define TRB_CH_FIELD control /* CH - Chain Bit */
#define TRB_CH_START 4
#define TRB_CH_LEN 1
#define TRB_IOC_FIELD control /* IOC - Interrupt On Completion */
#define TRB_IOC_START 5
#define TRB_IOC_LEN 1
#define TRB_IDT_FIELD control /* IDT - Immediate Data */
#define TRB_IDT_START 6
#define TRB_IDT_LEN 1
#define TRB_DC_FIELD control /* DC - Deconfigure */
#define TRB_DC_START 9
#define TRB_DC_LEN 1
#define TRB_TT_FIELD control /* TT - TRB Type */
#define TRB_TT_START 10
#define TRB_TT_LEN 6
#define TRB_TRT_FIELD control /* TRT - Transfer Type */
#define TRB_TRT_START 16
#define TRB_TRT_LEN 2
#define TRB_DIR_FIELD control /* DIR - Direction */
#define TRB_DIR_START 16
#define TRB_DIR_LEN 1
#define TRB_EP_FIELD control /* EP - Endpoint ID */
#define TRB_EP_START 16
#define TRB_EP_LEN 5
#define TRB_ID_FIELD control /* ID - Slot ID */
#define TRB_ID_START 24
#define TRB_ID_LEN 8
#define TRB_MASK(tok) MASK(TRB_##tok##_START, TRB_##tok##_LEN)
#define TRB_GET(tok, trb) (((trb)->TRB_##tok##_FIELD & TRB_MASK(tok)) \
>> TRB_##tok##_START)
#define TRB_SET(tok, trb, to) (trb)->TRB_##tok##_FIELD = \
(((trb)->TRB_##tok##_FIELD & ~TRB_MASK(tok)) | \
(((to) << TRB_##tok##_START) & TRB_MASK(tok)))
#define TRB_DUMP(tok, trb) usb_debug(" "#tok"\t0x%04"PRIx32"\n", TRB_GET(tok, trb))
#define TRB_CYCLE (1 << 0)
typedef volatile struct trb {
u32 ptr_low;
u32 ptr_high;
u32 status;
u32 control;
} trb_t;
#define EVENT_RING_SIZE 64
typedef struct {
trb_t *ring;
trb_t *cur;
trb_t *last;
u8 ccs;
u8 adv;
} event_ring_t;
#define TRANSFER_RING_SIZE 32
typedef struct {
trb_t *ring;
trb_t *cur;
u8 pcs;
} __attribute__ ((packed)) transfer_ring_t;
#define COMMAND_RING_SIZE 4
typedef transfer_ring_t command_ring_t;
#define SC_ROUTE_FIELD f1 /* ROUTE - Route String */
#define SC_ROUTE_START 0
#define SC_ROUTE_LEN 20
#define SC_SPEED_FIELD f1
#define SC_SPEED_START 20
#define SC_SPEED_LEN 4
#define SC_MTT_FIELD f1 /* MTT - Multi Transaction Translator */
#define SC_MTT_START 25
#define SC_MTT_LEN 1
#define SC_HUB_FIELD f1 /* HUB - Is this a hub? */
#define SC_HUB_START 26
#define SC_HUB_LEN 1
#define SC_CTXENT_FIELD f1 /* CTXENT - Context Entries (number of following ep contexts) */
#define SC_CTXENT_START 27
#define SC_CTXENT_LEN 5
#define SC_RHPORT_FIELD f2 /* RHPORT - Root Hub Port Number */
#define SC_RHPORT_START 16
#define SC_RHPORT_LEN 8
#define SC_NPORTS_FIELD f2 /* NPORTS - Number of Ports */
#define SC_NPORTS_START 24
#define SC_NPORTS_LEN 8
#define SC_TTID_FIELD f3 /* TTID - TT Hub Slot ID */
#define SC_TTID_START 0
#define SC_TTID_LEN 8
#define SC_TTPORT_FIELD f3 /* TTPORT - TT Port Number */
#define SC_TTPORT_START 8
#define SC_TTPORT_LEN 8
#define SC_TTT_FIELD f3 /* TTT - TT Think Time */
#define SC_TTT_START 16
#define SC_TTT_LEN 2
#define SC_UADDR_FIELD f4 /* UADDR - USB Device Address */
#define SC_UADDR_START 0
#define SC_UADDR_LEN 8
#define SC_STATE_FIELD f4 /* STATE - Slot State */
#define SC_STATE_START 27
#define SC_STATE_LEN 8
#define SC_MASK(tok) MASK(SC_##tok##_START, SC_##tok##_LEN)
#define SC_GET(tok, sc) (((sc).SC_##tok##_FIELD & SC_MASK(tok)) \
>> SC_##tok##_START)
#define SC_SET(tok, sc, to) (sc).SC_##tok##_FIELD = \
(((sc).SC_##tok##_FIELD & ~SC_MASK(tok)) | \
(((to) << SC_##tok##_START) & SC_MASK(tok)))
#define SC_DUMP(tok, sc) usb_debug(" "#tok"\t0x%04"PRIx32"\n", SC_GET(tok, sc))
typedef struct slotctx {
struct {
unsigned long Route_String:20;
unsigned long Speed:4;
unsigned long:1;
unsigned long MTT:1;
unsigned long Hub:1;
unsigned long Context_Entries:5;
} __attribute__ ((packed));
struct {
unsigned long Max_Exit_Latency:16;
unsigned long Root_Hub_Port_Number:8;
unsigned long Number_of_Ports:8;
} __attribute__ ((packed));
struct {
unsigned long TT_Hub_Slot_ID:8;
unsigned long TT_Port_Number:8;
unsigned long TTT:2;
unsigned long:4;
unsigned long Interrupter_Target:10;
} __attribute__ ((packed));
struct {
unsigned long USB_Device_Address:8;
unsigned long:19;
unsigned long Slot_State:5;
} __attribute__ ((packed));
u32 f1;
u32 f2;
u32 f3;
u32 f4;
u32 rsvd[4];
} slotctx_t;
#define EC_STATE_FIELD f1 /* STATE - Endpoint State */
#define EC_STATE_START 0
#define EC_STATE_LEN 3
#define EC_INTVAL_FIELD f1 /* INTVAL - Interval */
#define EC_INTVAL_START 16
#define EC_INTVAL_LEN 8
#define EC_CERR_FIELD f2 /* CERR - Error Count */
#define EC_CERR_START 1
#define EC_CERR_LEN 2
#define EC_TYPE_FIELD f2 /* TYPE - EP Type */
#define EC_TYPE_START 3
#define EC_TYPE_LEN 3
#define EC_MBS_FIELD f2 /* MBS - Max Burst Size */
#define EC_MBS_START 8
#define EC_MBS_LEN 8
#define EC_MPS_FIELD f2 /* MPS - Max Packet Size */
#define EC_MPS_START 16
#define EC_MPS_LEN 16
#define EC_DCS_FIELD tr_dq_low /* DCS - Dequeue Cycle State */
#define EC_DCS_START 0
#define EC_DCS_LEN 1
#define EC_AVRTRB_FIELD f5 /* AVRTRB - Average TRB Length */
#define EC_AVRTRB_START 0
#define EC_AVRTRB_LEN 16
#define EC_MXESIT_FIELD f5 /* MXESIT - Max ESIT Payload */
#define EC_MXESIT_START 16
#define EC_MXESIT_LEN 16
#define EC_MASK(tok) MASK(EC_##tok##_START, EC_##tok##_LEN)
#define EC_GET(tok, ec) (((ec).EC_##tok##_FIELD & EC_MASK(tok)) \
>> EC_##tok##_START)
#define EC_SET(tok, ec, to) (ec).EC_##tok##_FIELD = \
(((ec).EC_##tok##_FIELD & ~EC_MASK(tok)) | \
(((to) << EC_##tok##_START) & EC_MASK(tok)))
#define EC_DUMP(tok, ec) usb_debug(" "#tok"\t0x%04"PRIx32"\n", EC_GET(tok, ec))
enum { EP_ISOC_OUT = 1, EP_BULK_OUT = 2, EP_INTR_OUT = 3,
EP_CONTROL = 4, EP_ISOC_IN = 5, EP_BULK_IN = 6, EP_INTR_IN = 7 };
typedef struct epctx {
struct {
unsigned long EP_State:3;
unsigned long:5;
unsigned long Mult:2;
unsigned long MaxPStreams:5;
unsigned long LSA:1;
unsigned long Interval:8;
unsigned long:8;
} __attribute__ ((packed));
struct {
unsigned long:1;
unsigned long CErr:2;
unsigned long EP_Type:3;
unsigned long:1;
unsigned long HID:1;
unsigned long Max_Burst_Size:8;
unsigned long Max_Packet_Size:16;
} __attribute__ ((packed));
union {
u32 TR_Dequeue_Pointer_lo;
struct {
unsigned long DCS:1;
unsigned long:3;
} __attribute__ ((packed));
} __attribute__ ((packed));
u32 TR_Dequeue_Pointer_hi;
struct {
unsigned long Average_TRB_Length:16;
unsigned long Max_ESIT_Payload:16;
} __attribute__ ((packed));
u32 f1;
u32 f2;
u32 tr_dq_low;
u32 tr_dq_high;
u32 f5;
u32 rsvd[3];
} epctx_t;
typedef struct devctx {
slotctx_t slot;
epctx_t ep0;
typedef union devctx {
struct {
epctx_t out;
epctx_t in;
} eps[15];
slotctx_t slot;
epctx_t ep0;
epctx_t eps1_30[30];
};
epctx_t eps[32]; /* At index 0 it's actually the slotctx,
we have it like that so we can use
the ep_id directly as index. */
} devctx_t;
typedef struct devctxp {
devctx_t *ptr;
void *upper;
} devctxp_t;
typedef struct inputctx {
struct {
u32 drop;
u32 add;
u32 reserved[6];
} control;
devctx_t dev;
} inputctx_t;
typedef struct intrq {
size_t size; /* Size of each transfer */
size_t count; /* The number of TRBs to fill at once */
trb_t *next; /* The next TRB expected to be processed by the controller */
trb_t *ready; /* The last TRB in the transfer ring processed by the controller */
endpoint_t *ep;
} intrq_t;
typedef struct devinfo {
volatile devctx_t devctx;
transfer_ring_t *transfer_rings[32];
intrq_t *interrupt_queues[32];
} devinfo_t;
#define DEVINFO_FROM_XHCI(xhci, slot_id) \
(((xhci)->dcbaa[slot_id]) \
? phys_to_virt((xhci)->dcbaa[slot_id] - offsetof(devinfo_t, devctx)) \
: NULL)
typedef struct erst_entry {
u32 seg_base_lo;
@ -258,12 +368,14 @@ typedef struct xhci {
u32 usbcmd;
#define USBCMD_RS 1<<0
#define USBCMD_HCRST 1<<1
#define USBCMD_INTE 1<<2
u32 usbsts;
#define USBSTS_HCH 1<<0
#define USBSTS_HSE 1<<2
#define USBSTS_EINT 1<<3
#define USBSTS_PCD 1<<4
#define USBSTS_CNR 1<<11
#define USBSTS_PRSRV_MASK ((1 << 1) | 0xffffe000)
u32 pagesize;
u8 res1[0x13-0x0c+1];
u32 dnctrl;
@ -281,34 +393,35 @@ typedef struct xhci {
u8 res3[0x3ff-0x3c+1];
struct {
u32 portsc;
#define PORTSC_CCS 1<<0
#define PORTSC_PED 1<<1
#define PORTSC_CCS (1<<0)
#define PORTSC_PED (1<<1)
// BIT 2 rsvdZ
#define PORTSC_OCA 1<<3
#define PORTSC_PR 1<<4
#define PORTSC_PLS 1<<5
#define PORTSC_OCA (1<<3)
#define PORTSC_PR (1<<4)
#define PORTSC_PLS (1<<5)
#define PORTSC_PLS_MASK MASK(5, 4)
#define PORTSC_PP 1<<9
#define PORTSC_PORT_SPEED 1<<10
#define PORTSC_PORT_SPEED_MASK MASK(10, 4)
#define PORTSC_PIC 1<<14
#define PORTSC_PP (1<<9)
#define PORTSC_PORT_SPEED_START 10
#define PORTSC_PORT_SPEED (1<<PORTSC_PORT_SPEED_START)
#define PORTSC_PORT_SPEED_MASK MASK(PORTSC_PORT_SPEED_START, 4)
#define PORTSC_PIC (1<<14)
#define PORTSC_PIC_MASK MASK(14, 2)
#define PORTSC_LWS 1<<16
#define PORTSC_CSC 1<<17
#define PORTSC_PEC 1<<18
#define PORTSC_WRC 1<<19
#define PORTSC_OCC 1<<20
#define PORTSC_PRC 1<<21
#define PORTSC_PLC 1<<22
#define PORTSC_CEC 1<<23
#define PORTSC_CAS 1<<24
#define PORTSC_WCE 1<<25
#define PORTSC_WDE 1<<26
#define PORTSC_WOE 1<<27
#define PORTSC_LWS (1<<16)
#define PORTSC_CSC (1<<17)
#define PORTSC_PEC (1<<18)
#define PORTSC_WRC (1<<19)
#define PORTSC_OCC (1<<20)
#define PORTSC_PRC (1<<21)
#define PORTSC_PLC (1<<22)
#define PORTSC_CEC (1<<23)
#define PORTSC_CAS (1<<24)
#define PORTSC_WCE (1<<25)
#define PORTSC_WDE (1<<26)
#define PORTSC_WOE (1<<27)
// BIT 29:28 rsvdZ
#define PORTSC_DR 1<<30
#define PORTSC_WPR 1<<31
#define PORTSC_RW_MASK PORTSC_PR | PORTSC_PLS_MASK | PORTSC_PP | PORTSC_PIC_MASK | PORTSC_LWS | PORTSC_WCE | PORTSC_WDE | PORTSC_WOE
#define PORTSC_DR (1<<30)
#define PORTSC_WPR (1<<31)
#define PORTSC_RW_MASK (PORTSC_PR | PORTSC_PLS_MASK | PORTSC_PP | PORTSC_PIC_MASK | PORTSC_LWS | PORTSC_WCE | PORTSC_WDE | PORTSC_WOE)
u32 portpmsc;
u32 portli;
u32 res;
@ -335,16 +448,66 @@ typedef struct xhci {
volatile u32 *dbreg;
/* R/W, volatile, Memory -> bitfields allowed */
volatile devctxp_t *dcbaa;
u64 *dcbaa; /* pointers to sp_ptrs and output (device) contexts */
u64 *sp_ptrs; /* pointers to scratchpad buffers */
trb_t *cmd_ring;
trb_t *ev_ring;
command_ring_t cr;
event_ring_t er;
volatile erst_entry_t *ev_ring_table;
int cmd_ccs, ev_ccs;
usbdev_t *roothub;
u8 max_slots_en;
} xhci_t;
#define XHCI_INST(controller) ((xhci_t*)((controller)->instance))
void *xhci_align(const size_t min_align, const size_t size);
void xhci_init_cycle_ring(transfer_ring_t *, const size_t ring_size);
int xhci_set_address (hci_t *, int speed, int hubport, int hubaddr);
int xhci_finish_device_config(usbdev_t *);
void xhci_destroy_dev(hci_t *, int slot_id);
void xhci_reset_event_ring(event_ring_t *);
void xhci_advance_event_ring(xhci_t *);
void xhci_update_event_dq(xhci_t *);
void xhci_handle_events(xhci_t *);
int xhci_wait_for_command_aborted(xhci_t *, const trb_t *);
int xhci_wait_for_command_done(xhci_t *, const trb_t *, int clear_event);
int xhci_wait_for_transfer(xhci_t *, const int slot_id, const int ep_id);
void xhci_clear_trb(trb_t *, int pcs);
trb_t *xhci_next_command_trb(xhci_t *);
void xhci_post_command(xhci_t *);
int xhci_cmd_enable_slot(xhci_t *, int *slot_id);
int xhci_cmd_disable_slot(xhci_t *, int slot_id);
int xhci_cmd_address_device(xhci_t *, int slot_id, inputctx_t *);
int xhci_cmd_configure_endpoint(xhci_t *, int slot_id, int config_id, inputctx_t *);
int xhci_cmd_evaluate_context(xhci_t *, int slot_id, inputctx_t *);
int xhci_cmd_reset_endpoint(xhci_t *, int slot_id, int ep);
int xhci_cmd_stop_endpoint(xhci_t *, int slot_id, int ep);
int xhci_cmd_set_tr_dq(xhci_t *, int slot_id, int ep, trb_t *, int dcs);
static inline int xhci_ep_id(const endpoint_t *const ep) {
return ((ep->endpoint & 0x7f) << 1) + (ep->direction == IN);
}
#ifdef XHCI_DUMPS
void xhci_dump_slotctx(const slotctx_t *);
void xhci_dump_epctx(const epctx_t *);
void xhci_dump_devctx(const devctx_t *, const u32 ctx_mask);
void xhci_dump_inputctx(const inputctx_t *);
void xhci_dump_transfer_trb(const trb_t *);
void xhci_dump_transfer_trbs(const trb_t *first, const trb_t *last);
#else
#define xhci_dump_slotctx(args...) do {} while(0)
#define xhci_dump_epctx(args...) do {} while(0)
#define xhci_dump_devctx(args...) do {} while(0)
#define xhci_dump_inputctx(args...) do {} while(0)
#define xhci_dump_transfer_trb(args...) do {} while(0)
#define xhci_dump_transfer_trbs(args...) do {} while(0)
#endif
#endif

160
payloads/libpayload/drivers/usb/xhci_rh.c
View File

@ -1,7 +1,7 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2010 Patrick Georgi
* Copyright (C) 2013 secunet Security Networks AG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -29,105 +29,111 @@
#define USB_DEBUG
#include <libpayload.h>
#include <usb/usb.h>
#include "generic_hub.h"
#include "xhci_private.h"
#include "xhci.h"
typedef struct {
int numports;
int *port;
} rh_inst_t;
#define RH_INST(dev) ((rh_inst_t*)(dev)->data)
static void
xhci_rh_enable_port (usbdev_t *dev, int port)
static int
xhci_rh_hub_status_changed(usbdev_t *const dev)
{
// FIXME: check power situation?
// enable slot
// attach device context to slot
// address device
}
/* disable root hub */
static void
xhci_rh_disable_port (usbdev_t *dev, int port)
{
}
static void
xhci_rh_scanport (usbdev_t *dev, int port)
{
// clear CSC
int val = XHCI_INST (dev->controller)->opreg->prs[port].portsc;
val &= PORTSC_RW_MASK;
val |= PORTSC_CSC;
XHCI_INST (dev->controller)->opreg->prs[port].portsc = val;
usb_debug("device attach status on port %x: %x\n", port, XHCI_INST (dev->controller)->opreg->prs[port].portsc & PORTSC_CCS);
xhci_t *const xhci = XHCI_INST(dev->controller);
const int changed = !!(xhci->opreg->usbsts & USBSTS_PCD);
if (changed)
xhci->opreg->usbsts =
(xhci->opreg->usbsts & USBSTS_PRSRV_MASK) | USBSTS_PCD;
return changed;
}
static int
xhci_rh_report_port_changes (usbdev_t *dev)
xhci_rh_port_status_changed(usbdev_t *const dev, const int port)
{
int i;
// no change
if (!(XHCI_INST (dev->controller)->opreg->usbsts & USBSTS_PCD))
xhci_t *const xhci = XHCI_INST(dev->controller);
volatile u32 *const portsc = &xhci->opreg->prs[port - 1].portsc;
const int changed = !!(*portsc & PORTSC_CSC);
/* always clear all the status change bits */
*portsc = (*portsc & PORTSC_RW_MASK) | 0x00ef0000;
return changed;
}
static int
xhci_rh_port_connected(usbdev_t *const dev, const int port)
{
xhci_t *const xhci = XHCI_INST(dev->controller);
volatile u32 *const portsc = &xhci->opreg->prs[port - 1].portsc;
return *portsc & PORTSC_CCS;
}
static int
xhci_rh_port_in_reset(usbdev_t *const dev, const int port)
{
xhci_t *const xhci = XHCI_INST(dev->controller);
volatile u32 *const portsc = &xhci->opreg->prs[port - 1].portsc;
return !!(*portsc & PORTSC_PR);
}
static int
xhci_rh_port_enabled(usbdev_t *const dev, const int port)
{
xhci_t *const xhci = XHCI_INST(dev->controller);
volatile u32 *const portsc = &xhci->opreg->prs[port - 1].portsc;
return !!(*portsc & PORTSC_PED);
}
static int
xhci_rh_port_speed(usbdev_t *const dev, const int port)
{
xhci_t *const xhci = XHCI_INST(dev->controller);
volatile u32 *const portsc = &xhci->opreg->prs[port - 1].portsc;
if (*portsc & PORTSC_PED) {
return ((*portsc & PORTSC_PORT_SPEED_MASK)
>> PORTSC_PORT_SPEED_START)
- 1;
} else {
return -1;
for (i = 0; i < RH_INST (dev)->numports; i++) {
if (XHCI_INST (dev->controller)->opreg->prs[i].portsc & PORTSC_CSC) {
usb_debug("found connect status change on port %d\n", i);
return i;
}
}
return -1; // shouldn't ever happen
}
static void
xhci_rh_destroy (usbdev_t *dev)
static int
xhci_rh_start_port_reset(usbdev_t *const dev, const int port)
{
int i;
for (i = 0; i < RH_INST (dev)->numports; i++)
xhci_rh_disable_port (dev, i);
free (RH_INST (dev));
xhci_t *const xhci = XHCI_INST(dev->controller);
volatile u32 *const portsc = &xhci->opreg->prs[port - 1].portsc;
*portsc = (*portsc & PORTSC_RW_MASK) | PORTSC_PR;
return 0;
}
static void
xhci_rh_poll (usbdev_t *dev)
{
int port;
while ((port = xhci_rh_report_port_changes (dev)) != -1)
xhci_rh_scanport (dev, port);
}
static const generic_hub_ops_t xhci_rh_ops = {
.hub_status_changed = xhci_rh_hub_status_changed,
.port_status_changed = xhci_rh_port_status_changed,
.port_connected = xhci_rh_port_connected,
.port_in_reset = xhci_rh_port_in_reset,
.port_enabled = xhci_rh_port_enabled,
.port_speed = xhci_rh_port_speed,
.enable_port = NULL,
.disable_port = NULL,
.start_port_reset = xhci_rh_start_port_reset,
.reset_port = generic_hub_rh_resetport,
};
void
xhci_rh_init (usbdev_t *dev)
{
int i;
dev->destroy = xhci_rh_destroy;
dev->poll = xhci_rh_poll;
dev->data = malloc (sizeof (rh_inst_t));
if (!dev->data)
fatal("Not enough memory for XHCI RH.\n");
RH_INST (dev)->numports = XHCI_INST (dev->controller)->capreg->MaxPorts;
RH_INST (dev)->port = malloc(sizeof(int) * RH_INST (dev)->numports);
usb_debug("%d ports registered\n", RH_INST (dev)->numports);
for (i = 0; i < RH_INST (dev)->numports; i++) {
xhci_rh_enable_port (dev, i);
RH_INST (dev)->port[i] = -1;
}
/* we can set them here because a root hub _really_ shouldn't
appear elsewhere */
dev->address = 0;
dev->hub = -1;
dev->port = -1;
usb_debug("rh init done\n");
const int num_ports = /* TODO: maybe we need to read extended caps */
(XHCI_INST(dev->controller)->capreg->hcsparams1 >> 24) & 0xff;
generic_hub_init(dev, num_ports, &xhci_rh_ops);
usb_debug("xHCI: root hub init done\n");
}