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soc/intel: deduplicate acpi_fill_soc_wake 

The PM1_EN bits WAK_STS, RTC_EN, PWRBTN_EN don't need any SoC-specific
handling. Deduplicate `acpi_fill_soc_wake` by setting these bits in
common code.

Change-Id: I06628aeb5b82b30142a383b87c82a1e22a073ef5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Michael Niewöhner 2021-09-29 21:12:27 +02:00
parent fbcfb63b06
commit 9034689ee7
8 changed files with 1 additions and 105 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
src/soc/intel/alderlake/acpi.c
View File

@ -280,21 +280,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs)
sa_fill_gnvs(gnvs);
}
uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en,
const struct chipset_power_state *ps)
{
/*
* WAK_STS bit is set when the system is in one of the sleep states
* (via the SLP_EN bit) and an enabled wake event occurs. Upon setting
* this bit, the PMC will transition the system to the ON state and
* can only be set by hardware and can only be cleared by writing a one
* to this bit position.
*/
generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN;
return generic_pm1_en;
}
int soc_madt_sci_irq_polarity(int sci)
{
return MP_IRQ_POLARITY_HIGH;

15
src/soc/intel/apollolake/acpi.c
View File

@ -95,21 +95,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs)
sa_fill_gnvs(gnvs);
}
uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en,
const struct chipset_power_state *ps)
{
/*
* WAK_STS bit is set when the system is in one of the sleep states
* (via the SLP_EN bit) and an enabled wake event occurs. Upon setting
* this bit, the PMC will transition the system to the ON state and
* can only be set by hardware and can only be cleared by writing a one
* to this bit position.
*/
generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN;
return generic_pm1_en;
}
int soc_madt_sci_irq_polarity(int sci)
{
return MP_IRQ_POLARITY_LOW;

15
src/soc/intel/cannonlake/acpi.c
View File

@ -185,21 +185,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs)
sa_fill_gnvs(gnvs);
}
uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en,
const struct chipset_power_state *ps)
{
/*
* WAK_STS bit is set when the system is in one of the sleep states
* (via the SLP_EN bit) and an enabled wake event occurs. Upon setting
* this bit, the PMC will transition the system to the ON state and
* can only be set by hardware and can only be cleared by writing a one
* to this bit position.
*/
generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN;
return generic_pm1_en;
}
int soc_madt_sci_irq_polarity(int sci)
{
return MP_IRQ_POLARITY_HIGH;

1
src/soc/intel/common/block/acpi/acpi.c
View File

@ -218,6 +218,7 @@ int soc_fill_acpi_wake(const struct chipset_power_state *ps, uint32_t *pm1, uint
* powerbtn or any other wake source like lidopen, key board press etc.
*/
pm1_en = ps->pm1_en;
pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN;
pm1_en = acpi_fill_soc_wake(pm1_en, ps);

15
src/soc/intel/elkhartlake/acpi.c
View File

@ -249,21 +249,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs)
sa_fill_gnvs(gnvs);
}
uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en,
const struct chipset_power_state *ps)
{
/*
* WAK_STS bit is set when the system is in one of the sleep states
* (via the SLP_EN bit) and an enabled wake event occurs. Upon setting
* this bit, the PMC will transition the system to the ON state and
* can only be set by hardware and can only be cleared by writing a one
* to this bit position.
*/
generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN;
return generic_pm1_en;
}
int soc_madt_sci_irq_polarity(int sci)
{
return MP_IRQ_POLARITY_HIGH;

15
src/soc/intel/icelake/acpi.c
View File

@ -180,21 +180,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs)
sa_fill_gnvs(gnvs);
}
uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en,
const struct chipset_power_state *ps)
{
/*
* WAK_STS bit is set when the system is in one of the sleep states
* (via the SLP_EN bit) and an enabled wake event occurs. Upon setting
* this bit, the PMC will transition the system to the ON state and
* can only be set by hardware and can only be cleared by writing a one
* to this bit position.
*/
generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN;
return generic_pm1_en;
}
int soc_madt_sci_irq_polarity(int sci)
{
return MP_IRQ_POLARITY_HIGH;

15
src/soc/intel/jasperlake/acpi.c
View File

@ -260,21 +260,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs)
sa_fill_gnvs(gnvs);
}
uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en,
const struct chipset_power_state *ps)
{
/*
* WAK_STS bit is set when the system is in one of the sleep states
* (via the SLP_EN bit) and an enabled wake event occurs. Upon setting
* this bit, the PMC will transition the system to the ON state and
* can only be set by hardware and can only be cleared by writing a one
* to this bit position.
*/
generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN;
return generic_pm1_en;
}
int soc_madt_sci_irq_polarity(int sci)
{
return MP_IRQ_POLARITY_HIGH;

15
src/soc/intel/tigerlake/acpi.c
View File

@ -275,21 +275,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs)
sa_fill_gnvs(gnvs);
}
uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en,
const struct chipset_power_state *ps)
{
/*
* WAK_STS bit is set when the system is in one of the sleep states
* (via the SLP_EN bit) and an enabled wake event occurs. Upon setting
* this bit, the PMC will transition the system to the ON state and
* can only be set by hardware and can only be cleared by writing a one
* to this bit position.
*/
generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN;
return generic_pm1_en;
}
int soc_madt_sci_irq_polarity(int sci)
{
return MP_IRQ_POLARITY_HIGH;