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soc/intel/cannonlake: Change LPDDR4 to MEMCFG 

Modify the previously SOC_CNL_LPDDR4_INIT to SOC_CNL_MEMCFG_INIT, to
make the infrasturture to handle both LPDDR4 and DDR4 cases in the
future. Consider the case of reading SPD from SMBus other than providing
SPD pointer directly.

BUG=N/A
TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a"
compiles successfully.

Change-Id: I2f898147f67dd52b89cc3d9fc4e6b3854fa81f57
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28248
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Lijian Zhao 2018-08-20 14:06:13 -07:00 committed by Martin Roth
parent 5dff396bef
commit 903c9764a1
9 changed files with 92 additions and 65 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/google/zoombini/Kconfig
View File

@ -12,7 +12,7 @@ config BOARD_GOOGLE_BASEBOARD_ZOOMBINI
select HAVE_ACPI_TABLES
select MAINBOARD_HAS_CHROMEOS
select SOC_INTEL_CANNONLAKE
select SOC_INTEL_CANNONLAKE_LPDDR4_INIT
select SOC_INTEL_CANNONLAKE_MEMCFG_INIT
if BOARD_GOOGLE_BASEBOARD_ZOOMBINI

14
src/mainboard/google/zoombini/memory.c
View File

@ -17,10 +17,10 @@
#include <baseboard/gpio.h>
#include <compiler.h>
#include <gpio.h>
#include <soc/cnl_lpddr4_init.h>
#include <soc/cnl_memcfg_init.h>
static const struct lpddr4_cfg baseboard_lpddr4_cfg = {
.dq_map[LP4_CH0] = {
static const struct cnl_mb_cfg baseboard_lpddr4_cfg = {
.dq_map[DDR_CH0] = {
/*
* CLK0 goes to package 0 - Bytes[3:0],
* CLK1 goes to package 1 - Bytes[7:4]
@ -37,7 +37,7 @@ static const struct lpddr4_cfg baseboard_lpddr4_cfg = {
{ 0xFF, 0x00 },
},
.dq_map[LP4_CH1] = {
.dq_map[DDR_CH1] = {
/*
* CLK0 goes to package 0 - Bytes[3:0],
* CLK1 goes to package 1 - Bytes[7:4]
@ -61,8 +61,8 @@ static const struct lpddr4_cfg baseboard_lpddr4_cfg = {
* the index = pin number on lpddr4 part
* the value = pin number on SoC
*/
.dqs_map[LP4_CH0] = { 3, 1, 2, 0, 7, 5, 6, 4 },
.dqs_map[LP4_CH1] = { 3, 2, 0, 1, 7, 5, 6, 4 },
.dqs_map[DDR_CH0] = { 3, 1, 2, 0, 7, 5, 6, 4 },
.dqs_map[DDR_CH1] = { 3, 2, 0, 1, 7, 5, 6, 4 },
/* Baseboard uses three 100 Ohm rcomp resistors */
.rcomp_resistor = { 100, 100, 100 },
@ -82,7 +82,7 @@ static const struct lpddr4_cfg baseboard_lpddr4_cfg = {
.ect = 0,
};
const struct lpddr4_cfg *__weak variant_lpddr4_config(void)
const struct cnl_mb_cfg *__weak variant_lpddr4_config(void)
{
return &baseboard_lpddr4_cfg;
}

4
src/mainboard/google/zoombini/romstage.c
View File

@ -14,7 +14,7 @@
*/
#include <baseboard/variants.h>
#include <soc/cnl_lpddr4_init.h>
#include <soc/cnl_memcfg_init.h>
#include <soc/romstage.h>
void mainboard_memory_init_params(FSPM_UPD *memupd)
@ -24,6 +24,6 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
.spd_spec.spd_index = variant_memory_sku(),
};
cannonlake_lpddr4_init(&memupd->FspmConfig,
cannonlake_memcfg_init(&memupd->FspmConfig,
variant_lpddr4_config(), &spd);
}

4
src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h
View File

@ -17,7 +17,7 @@
#ifndef __BASEBOARD_VARIANTS_H__
#define __BASEBOARD_VARIANTS_H__
#include <soc/cnl_lpddr4_init.h>
#include <soc/cnl_memcfg_init.h>
#include <soc/gpio.h>
#include <stdint.h>
#include <vendorcode/google/chromeos/chromeos.h>
@ -35,7 +35,7 @@ const struct pad_config *variant_early_gpio_table(size_t *num);
const struct cros_gpio *variant_cros_gpios(size_t *num);
/* Return LPDDR4 configuration structure. */
const struct lpddr4_cfg *variant_lpddr4_config(void);
const struct cnl_mb_cfg *variant_lpddr4_config(void);
/* Return memory SKU for the board. */
size_t variant_memory_sku(void);

14
src/mainboard/google/zoombini/variants/meowth/memory.c
View File

@ -16,10 +16,10 @@
#include <baseboard/variants.h>
#include <baseboard/gpio.h>
#include <gpio.h>
#include <soc/cnl_lpddr4_init.h>
#include <soc/cnl_memcfg_init.h>
static const struct lpddr4_cfg meowth_lpddr4_cfg = {
.dq_map[LP4_CH0] = {
static const struct cnl_mb_cfg meowth_lpddr4_cfg = {
.dq_map[DDR_CH0] = {
/*
* CLK0 goes to package 0 - Bytes[3:0],
* CLK1 goes to package 1 - Bytes[7:4]
@ -36,7 +36,7 @@ static const struct lpddr4_cfg meowth_lpddr4_cfg = {
{ 0xFF, 0x00 },
},
.dq_map[LP4_CH1] = {
.dq_map[DDR_CH1] = {
/*
* CLK0 goes to package 0 - Bytes[3:0],
* CLK1 goes to package 1 - Bytes[7:4]
@ -65,8 +65,8 @@ static const struct lpddr4_cfg meowth_lpddr4_cfg = {
* and it will translate that and display 8 values per channel.
* Those values are copied into the dqs_map arrays below.
*/
.dqs_map[LP4_CH0] = { 3, 1, 2, 0, 7, 5, 6, 4 },
.dqs_map[LP4_CH1] = { 2, 3, 1, 0, 7, 5, 6, 4 },
.dqs_map[DDR_CH0] = { 3, 1, 2, 0, 7, 5, 6, 4 },
.dqs_map[DDR_CH1] = { 2, 3, 1, 0, 7, 5, 6, 4 },
/* Meowth uses three 100 Ohm rcomp resistors */
.rcomp_resistor = { 100, 100, 100 },
@ -86,7 +86,7 @@ static const struct lpddr4_cfg meowth_lpddr4_cfg = {
.ect = 1,
};
const struct lpddr4_cfg *variant_lpddr4_config(void)
const struct cnl_mb_cfg *variant_lpddr4_config(void)
{
return &meowth_lpddr4_cfg;
}

2
src/soc/intel/cannonlake/Kconfig
View File

@ -184,7 +184,7 @@ config CPU_BCLK_MHZ
int
default 100
config SOC_INTEL_CANNONLAKE_LPDDR4_INIT
config SOC_INTEL_CANNONLAKE_MEMCFG_INIT
bool
default n

2
src/soc/intel/cannonlake/Makefile.inc
View File

@ -22,7 +22,7 @@ bootblock-y += lpc.c
bootblock-y += p2sb.c
bootblock-$(CONFIG_UART_DEBUG) += uart.c
romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_LPDDR4_INIT) += cnl_lpddr4_init.c
romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_MEMCFG_INIT) += cnl_memcfg_init.c
romstage-y += gpio.c
romstage-y += gspi.c
romstage-y += i2c.c

76
src/soc/intel/cannonlake/cnl_lpddr4_init.c → src/soc/intel/cannonlake/cnl_memcfg_init.c
View File

@ -15,13 +15,12 @@
#include <assert.h>
#include <console/console.h>
#include <fsp/util.h>
#include <soc/cnl_lpddr4_init.h>
#include <soc/cnl_memcfg_init.h>
#include <spd_bin.h>
#include <string.h>
static void meminit_lpddr4(FSP_M_CONFIG *mem_cfg,
const struct lpddr4_cfg *board_cfg,
size_t spd_data_len, uintptr_t spd_data_ptr)
static void meminit_memcfg(FSP_M_CONFIG *mem_cfg,
const struct cnl_mb_cfg *board_cfg)
{
/*
* DqByteMapChx expects 12 bytes of data, but the last 6 bytes
@ -29,17 +28,17 @@ static void meminit_lpddr4(FSP_M_CONFIG *mem_cfg,
* we null out the rest of the data.
*/
memset(&mem_cfg->DqByteMapCh0, 0, sizeof(mem_cfg->DqByteMapCh0));
memcpy(&mem_cfg->DqByteMapCh0, &board_cfg->dq_map[LP4_CH0],
sizeof(board_cfg->dq_map[LP4_CH0]));
memcpy(&mem_cfg->DqByteMapCh0, &board_cfg->dq_map[DDR_CH0],
sizeof(board_cfg->dq_map[DDR_CH0]));
memset(&mem_cfg->DqByteMapCh1, 0, sizeof(mem_cfg->DqByteMapCh1));
memcpy(&mem_cfg->DqByteMapCh1, &board_cfg->dq_map[LP4_CH1],
sizeof(board_cfg->dq_map[LP4_CH1]));
memcpy(&mem_cfg->DqByteMapCh1, &board_cfg->dq_map[DDR_CH1],
sizeof(board_cfg->dq_map[DDR_CH1]));
memcpy(&mem_cfg->DqsMapCpu2DramCh0, &board_cfg->dqs_map[LP4_CH0],
sizeof(board_cfg->dqs_map[LP4_CH0]));
memcpy(&mem_cfg->DqsMapCpu2DramCh1, &board_cfg->dqs_map[LP4_CH1],
sizeof(board_cfg->dqs_map[LP4_CH1]));
memcpy(&mem_cfg->DqsMapCpu2DramCh0, &board_cfg->dqs_map[DDR_CH0],
sizeof(board_cfg->dqs_map[DDR_CH0]));
memcpy(&mem_cfg->DqsMapCpu2DramCh1, &board_cfg->dqs_map[DDR_CH1],
sizeof(board_cfg->dqs_map[DDR_CH1]));
memcpy(&mem_cfg->RcompResistor, &board_cfg->rcomp_resistor,
sizeof(mem_cfg->RcompResistor));
@ -47,7 +46,12 @@ static void meminit_lpddr4(FSP_M_CONFIG *mem_cfg,
/* Early cannonlake requires rcomp targets to be 0 */
memcpy(&mem_cfg->RcompTarget, &board_cfg->rcomp_targets,
sizeof(mem_cfg->RcompTarget));
}
static void meminit_memcfg_spd(FSP_M_CONFIG *mem_cfg,
const struct cnl_mb_cfg *board_cfg,
size_t spd_data_len, uintptr_t spd_data_ptr)
{
mem_cfg->MemorySpdDataLen = spd_data_len;
mem_cfg->MemorySpdPtr00 = spd_data_ptr;
@ -56,23 +60,23 @@ static void meminit_lpddr4(FSP_M_CONFIG *mem_cfg,
}
/*
* Initialize default LPDDR4 settings using spd data contained in a buffer.
* Initialize default memory settings using spd data contained in a buffer.
*/
static void meminit_lpddr4_spd_data(FSP_M_CONFIG *mem_cfg,
const struct lpddr4_cfg *cnl_cfg,
static void meminit_spd_data(FSP_M_CONFIG *mem_cfg,
const struct cnl_mb_cfg *cnl_cfg,
size_t spd_data_len, uintptr_t spd_data_ptr)
{
assert(spd_data_ptr && spd_data_len);
meminit_lpddr4(mem_cfg, cnl_cfg, spd_data_len, spd_data_ptr);
meminit_memcfg_spd(mem_cfg, cnl_cfg, spd_data_len, spd_data_ptr);
}
/*
* Initialize default LPDDR4 settings using the spd file specified by
* Initialize default memory settings using the spd file specified by
* spd_index. The spd_index is an index into the SPD_SOURCES array defined
* in spd/Makefile.inc.
*/
static void meminit_lpddr4_cbfs_spd_index(FSP_M_CONFIG *mem_cfg,
const struct lpddr4_cfg *cnl_cfg,
static void meminit_cbfs_spd_index(FSP_M_CONFIG *mem_cfg,
const struct cnl_mb_cfg *cnl_cfg,
int spd_index)
{
size_t spd_data_len;
@ -86,26 +90,40 @@ static void meminit_lpddr4_cbfs_spd_index(FSP_M_CONFIG *mem_cfg,
/* Memory leak is ok since we have memory mapped boot media */
assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED));
spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev);
meminit_lpddr4_spd_data(mem_cfg, cnl_cfg, spd_data_len, spd_data_ptr);
meminit_spd_data(mem_cfg, cnl_cfg, spd_data_len, spd_data_ptr);
}
/* Initialize LPDDR4 settings for CannonLake */
void cannonlake_lpddr4_init(FSP_M_CONFIG *mem_cfg,
const struct lpddr4_cfg *cnl_cfg,
/* Initialize onboard memory configurations for CannonLake */
void cannonlake_memcfg_init(FSP_M_CONFIG *mem_cfg,
const struct cnl_mb_cfg *cnl_cfg,
const struct spd_info *spd)
{
bool OnModuleSpd;
/* Early Command Training Enabled */
mem_cfg->ECT = cnl_cfg->ect;
mem_cfg->DqPinsInterleaved = cnl_cfg->dq_pins_interleaved;
mem_cfg->RefClk = 0; /* Auto Select CLK freq */
mem_cfg->CaVrefConfig = 0; /* VREF_CA->CHA/CHB */
mem_cfg->CaVrefConfig = cnl_cfg->vref_ca_config;
if (spd->spd_by_index) {
meminit_lpddr4_cbfs_spd_index(mem_cfg, cnl_cfg,
/* Spd pointer will only be used if all smbus slave address of memory
* sockets on the platform is empty */
for (int i = 0; i < ARRAY_SIZE(mem_cfg->SpdAddressTable); i++) {
if (spd->spd_smbus_address[i] != 0) {
mem_cfg->SpdAddressTable[i] = spd->spd_smbus_address[i];
OnModuleSpd = 1;
}
}
if (!OnModuleSpd) {
if (spd->spd_by_index) {
meminit_cbfs_spd_index(mem_cfg, cnl_cfg,
spd->spd_spec.spd_index);
} else {
meminit_lpddr4_spd_data(mem_cfg, cnl_cfg,
} else {
meminit_spd_data(mem_cfg, cnl_cfg,
spd->spd_spec.spd_data_ptr_info.spd_data_len,
spd->spd_spec.spd_data_ptr_info.spd_data_ptr);
}
}
meminit_memcfg(mem_cfg, cnl_cfg);
}

39
src/soc/intel/cannonlake/include/soc/cnl_lpddr4_init.h → src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h
View File

@ -13,8 +13,8 @@
* GNU General Public License for more details.
*/
#ifndef _SOC_CANNONLAKE_LPDDR4_INIT_H_
#define _SOC_CANNONLAKE_LPDDR4_INIT_H_
#ifndef _SOC_CANNONLAKE_MEMCFG_INIT_H_
#define _SOC_CANNONLAKE_MEMCFG_INIT_H_
#include <stddef.h>
#include <stdint.h>
@ -24,15 +24,15 @@
#define DQ_BITS_PER_DQS 8
/*
* Number of LPDDR4 packages, where a "package" represents a 64-bit solution.
* Number of memory packages, where a "package" represents a 64-bit solution.
*/
#define LP4_NUM_PACKAGES 2
#define DDR_NUM_PACKAGES 2
/* 64-bit Channel identification */
enum {
LP4_CH0,
LP4_CH1,
LP4_NUM_CHANNELS
DDR_CH0,
DDR_CH1,
DDR_NUM_CHANNELS
};
struct spd_by_pointer {
@ -46,10 +46,11 @@ struct spd_info {
int spd_index;
struct spd_by_pointer spd_data_ptr_info;
} spd_spec;
const uint8_t spd_smbus_address[4];
};
/* Board-specific lpddr4 dq mapping information */
struct lpddr4_cfg {
/* Board-specific memory dq mapping information */
struct cnl_mb_cfg {
/*
* For each channel, there are 3 sets of DQ byte mappings,
* where each set has a package 0 and a package 1 value (package 0
@ -61,7 +62,7 @@ struct lpddr4_cfg {
* and let the meminit_lpddr4() routine take care of clearing the
* unused fields for the caller.
*/
const uint8_t dq_map[LP4_NUM_CHANNELS][3][LP4_NUM_PACKAGES];
const uint8_t dq_map[DDR_NUM_CHANNELS][3][DDR_NUM_PACKAGES];
/*
* DQS CPU<>DRAM map Ch0 and Ch1. Each array entry represents a
@ -70,7 +71,7 @@ struct lpddr4_cfg {
* on the memory part, and the values in the array represent which
* pin on the CPU that DRAM pin connects to.
*/
const uint8_t dqs_map[LP4_NUM_CHANNELS][DQ_BITS_PER_DQS];
const uint8_t dqs_map[DDR_NUM_CHANNELS][DQ_BITS_PER_DQS];
/*
* Rcomp resistor values. These values represent the resistance in
@ -92,15 +93,23 @@ struct lpddr4_cfg {
*/
const uint8_t dq_pins_interleaved;
/*
* VREF_CA configuraation.
* Set to 0 VREF_CA goes to both CH_A and CH_B,
* set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B,
* set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B.
*/
const uint8_t vref_ca_config;
/* Early Command Training Enabled */
const uint8_t ect;
};
/*
* Initialize default LPDDR4 settings for CannonLake.
* Initialize default memory configurations for CannonLake.
*/
void cannonlake_lpddr4_init(FSP_M_CONFIG *mem_cfg,
const struct lpddr4_cfg *cnl_cfg,
void cannonlake_memcfg_init(FSP_M_CONFIG *mem_cfg,
const struct cnl_mb_cfg *cnl_cfg,
const struct spd_info *spd);
#endif /* _SOC_CANNONLAKE_LPDDR4_INIT_H_ */
#endif /* _SOC_CANNONLAKE_MEMCFG_INIT_H_ */