binaryPI: Introduce BINARYPI_LEGACY_WRAPPER and its counterpart

We define BINARYPI_LEGACY_WRAPPER a method of calling AGESA
via functions in agesawrapper.c file. The approach implemented
there makes it very inconvenient to do board-specific
customisation or present common platform-specific features.
Seems like it also causes assertion errors on AGESA side.
The flag is applied here to all boards and then individually
removed one at a time, as things get tested.

New method is not to call AGESA internal functions directly,
but via the dispatcher. AGESA call parameters are routed to
hooks in both platform and board -directories, to allow for
easy capture or modification as needed.

For each AGESA dispatcher call made, eventlog entries are
replayed to the console log. Also relocations of AGESA heap
that took place are recorded.

New method is expected to be compatible with binaryPI.

Change-Id: I2900249e60f21a13dc231f4a8a04835e090109d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/cpu/amd/agesa/romstage.c

@@ -131,7 +131,7 @@ void asmlinkage romstage_after_car(void)
 	if (HAS_LEGACY_WRAPPER)
 		agesa_postcar(cb);
 
-	if (cb->s3resume)
+	if (!IS_ENABLED(CONFIG_CPU_AMD_PI) && cb->s3resume)
 		set_resume_cache();
 
 	run_ramstage();

src/cpu/amd/pi/Kconfig

@@ -30,6 +30,9 @@ config CPU_AMD_PI
 
 if CPU_AMD_PI
 
+config BINARYPI_LEGACY_WRAPPER
+	def_bool n
+
 config XIP_ROM_SIZE
 	hex
 	default 0x100000

src/cpu/amd/pi/Makefile.inc

@@ -19,7 +19,12 @@ subdirs-$(CONFIG_CPU_AMD_PI_00660F01) += 00660F01
 
 cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram.inc
 
+ifeq ($(CONFIG_BINARYPI_LEGACY_WRAPPER), y)
 romstage-y += romstage.c
+ramstage-y += amd_late_init.c
+else
+romstage-y += ../agesa/romstage.c
+endif
+
 romstage-y += ../agesa/heapmanager.c
 ramstage-y += ../agesa/heapmanager.c
-ramstage-y += amd_late_init.c

src/mainboard/amd/bettong/Kconfig

@@ -17,6 +17,7 @@ if BOARD_AMD_BETTONG
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
+	select BINARYPI_LEGACY_WRAPPER
 	select CPU_AMD_PI_00660F01
 	select NORTHBRIDGE_AMD_PI_00660F01
 	select SOUTHBRIDGE_AMD_PI_KERN

src/mainboard/amd/db-ft3b-lc/Kconfig

@@ -18,6 +18,7 @@ if BOARD_AMD_DB_FT3B_LC
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
+	select BINARYPI_LEGACY_WRAPPER
 	select CPU_AMD_PI_00730F01
 	select NORTHBRIDGE_AMD_PI_00730F01
 	select SOUTHBRIDGE_AMD_PI_AVALON

src/mainboard/amd/lamar/Kconfig

@@ -17,6 +17,7 @@ if BOARD_AMD_LAMAR
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
+	select BINARYPI_LEGACY_WRAPPER
 	select CPU_AMD_PI_00630F01
 	select NORTHBRIDGE_AMD_PI_00630F01
 	select SOUTHBRIDGE_AMD_PI_BOLTON

src/mainboard/amd/olivehillplus/Kconfig

@@ -17,6 +17,7 @@ if BOARD_AMD_OLIVEHILLPLUS
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
+	select BINARYPI_LEGACY_WRAPPER
 	select CPU_AMD_PI_00730F01
 	select NORTHBRIDGE_AMD_PI_00730F01
 	select SOUTHBRIDGE_AMD_PI_AVALON

src/mainboard/bap/ode_e21XX/Kconfig

@@ -17,6 +17,7 @@ if BOARD_ODE_E21XX
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
+	select BINARYPI_LEGACY_WRAPPER
 	select CPU_AMD_PI_00730F01
 	select NORTHBRIDGE_AMD_PI_00730F01
 	select SOUTHBRIDGE_AMD_PI_AVALON

src/mainboard/pcengines/apu2/Kconfig

@@ -18,6 +18,7 @@ if BOARD_PCENGINES_APU2
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
+	select BINARYPI_LEGACY_WRAPPER
 	select CPU_AMD_PI_00730F01
 	select NORTHBRIDGE_AMD_PI_00730F01
 	select SOUTHBRIDGE_AMD_PI_AVALON

src/northbridge/amd/agesa/agesawrapper.h

@@ -16,7 +16,8 @@
 #ifndef _AGESAWRAPPER_H_
 #define _AGESAWRAPPER_H_
 
-#if IS_ENABLED(CONFIG_AGESA_LEGACY_WRAPPER) || IS_ENABLED(CONFIG_CPU_AMD_PI)
+#if IS_ENABLED(CONFIG_AGESA_LEGACY_WRAPPER) || \
+	IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
 
 #include <stdint.h>
 #include "Porting.h"
@@ -65,7 +66,7 @@ struct OEM_HOOK
 extern const struct OEM_HOOK OemCustomize;
 #endif
 
-#if IS_ENABLED(CONFIG_CPU_AMD_PI)
+#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
 const void *agesawrapper_locate_module (const CHAR8 name[8]);
 
 VOID OemCustomizeInitEarly (IN OUT AMD_EARLY_PARAMS *InitEarly);

src/northbridge/amd/agesa/eventlog.c

@@ -38,12 +38,28 @@ static const char *HeapStatusStr[] = {
 	"DoNotExistYet", "LocalCache", "TempMem", "SystemMem", "DoNotExistAnymore","S3Resume"
 };
 
+/* This function has to match with enumeration of AGESA_STRUCT_NAME defined
+ * inside AMD.h header file. Unfortunately those are different across
+ * different vendorcode subtrees.
+ *
+ * TBD: Fix said header or move this function together with the strings above
+ * under vendorcode/ tree.
+ */
+
 const char *agesa_struct_name(int state)
 {
+#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_OPENSOURCE)
 	if ((state < AMD_INIT_RECOVERY) || (state > AMD_IDENTIFY_DIMMS))
 		return undefined;
 
 	int index = state - AMD_INIT_RECOVERY;
+#else
+	state >>= 12;
+	if ((state < AMD_INIT_RECOVERY >> 12) || (state > AMD_IDENTIFY_DIMMS >> 12))
+		return undefined;
+
+	int index = state - (AMD_INIT_RECOVERY >> 12);
+#endif
 	return AgesaFunctionNameStr[index];
 }
 

src/northbridge/amd/agesa/state_machine.h

@@ -21,7 +21,7 @@
 #include <AMD.h>
 
 #define HAS_LEGACY_WRAPPER (IS_ENABLED(CONFIG_AGESA_LEGACY_WRAPPER) || \
-	IS_ENABLED(CONFIG_CPU_AMD_PI))
+	IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER))
 
 /* eventlog */
 const char *agesa_struct_name(int state);
@@ -99,7 +99,10 @@ void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save);
 #define HAS_AGESA_FCH_OEM_CALLOUT \
 	IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) || \
 	IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) || \
-	IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON)
+	IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || \
+	IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) || \
+	IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) || \
+	IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN)
 
 #if HAS_AGESA_FCH_OEM_CALLOUT
 /* FIXME:  Structures included here were supposed to be private to AGESA. */

src/northbridge/amd/pi/00630F01/northbridge.c

@@ -35,8 +35,10 @@
 #include <cpu/amd/amdfam15.h>
 #include <cpuRegisters.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
+#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
 #include <northbridge/amd/pi/agesawrapper.h>
 #include <northbridge/amd/pi/agesawrapper_call.h>
+#endif
 #include "northbridge.h"
 
 #include <cpu/x86/lapic.h>
@@ -630,6 +632,7 @@ static void domain_read_resources(device_t dev)
 
 static void domain_enable_resources(device_t dev)
 {
+#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
 	/* Must be called after PCI enumeration and resource allocation */
 	if (!acpi_is_wakeup_s3()) {
 		/* Enable MMIO on AMD CPU Address Map Controller */
@@ -638,6 +641,7 @@ static void domain_enable_resources(device_t dev)
 		agesawrapper_amdinitmid();
 	}
 	printk(BIOS_DEBUG, "  ader - leaving %s.\n", __func__);
+#endif
 }
 
 #if CONFIG_HW_MEM_HOLE_SIZEK != 0

src/northbridge/amd/pi/00660F01/northbridge.c

@@ -35,8 +35,10 @@
 #include <cpu/amd/amdfam15.h>
 #include <cpuRegisters.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
+#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
 #include <northbridge/amd/pi/agesawrapper.h>
 #include <northbridge/amd/pi/agesawrapper_call.h>
+#endif
 #include "northbridge.h"
 
 #include <cpu/x86/lapic.h>
@@ -635,11 +637,13 @@ static void domain_read_resources(device_t dev)
 
 static void domain_enable_resources(device_t dev)
 {
+#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
 	/* Must be called after PCI enumeration and resource allocation */
 	if (!acpi_is_wakeup_s3())
 		AGESAWRAPPER(amdinitmid);
 
 	printk(BIOS_DEBUG, "  ader - leaving domain_enable_resources.\n");
+#endif
 }
 
 #if CONFIG_HW_MEM_HOLE_SIZEK != 0

src/northbridge/amd/pi/00730F01/northbridge.c

@@ -35,8 +35,10 @@
 #include <cpu/amd/amdfam16.h>
 #include <cpuRegisters.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
+#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
 #include <northbridge/amd/pi/agesawrapper.h>
 #include <northbridge/amd/pi/agesawrapper_call.h>
+#endif
 #include "northbridge.h"
 
 #include <cpu/x86/lapic.h>
@@ -649,11 +651,13 @@ static void domain_read_resources(device_t dev)
 
 static void domain_enable_resources(device_t dev)
 {
+#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
 	/* Must be called after PCI enumeration and resource allocation */
 	if (!acpi_is_wakeup_s3())
 		AGESAWRAPPER(amdinitmid);
 
 	printk(BIOS_DEBUG, "  ader - leaving domain_enable_resources.\n");
+#endif
 }
 
 #if CONFIG_HW_MEM_HOLE_SIZEK != 0

src/northbridge/amd/pi/Makefile.inc

@@ -19,8 +19,17 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00630F01) += 00630F01
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00730F01) += 00730F01
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00660F01) += 00660F01
 
+ifeq ($(CONFIG_BINARYPI_LEGACY_WRAPPER), y)
 romstage-y += agesawrapper.c
 ramstage-y += agesawrapper.c
+else
+romstage-y += ../agesa/state_machine.c
+ramstage-y += ../agesa/state_machine.c
+
+romstage-y += ../agesa/eventlog.c
+ramstage-y += ../agesa/eventlog.c
+
+endif
 
 romstage-y += ../agesa/def_callouts.c ../agesa/eventlog.c
 ramstage-y += ../agesa/def_callouts.c ../agesa/eventlog.c ../agesa/acpi_tables.c

src/vendorcode/amd/pi/Makefile.inc

@@ -111,7 +111,11 @@ $(call src-to-obj,libagesa,$1): $(agesa_src_path)/$(notdir $1) $(obj)/config.h $
 endef
 
 agesa_raw_files += $(wildcard $(src)/vendorcode/amd/pi/Lib/*.[cS])
+
+ifeq ($(CONFIG_BINARYPI_LEGACY_WRAPPER)$(CONFIG_SOC_AMD_PI),y)
 agesa_raw_files += $(wildcard $(AGESA_ROOT)/binaryPI/*.[cS])
+endif
+
 ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y)
 agesa_raw_files += $(wildcard $(AGESA_ROOT)/Proc/Fch/Kern/KernImc/*.[cS])
 agesa_raw_files += $(wildcard $(AGESA_ROOT)/Proc/Fch/Common/*.[cS])