From 9065f4f8ed2facb60df3f4906b8e1e66e8958379 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Sat, 21 Nov 2020 02:12:54 +0100 Subject: [PATCH] soc/amd: move non-CAR linker scripts to common directory AMD family 17h and newer don't use cache as RAM, since the RAM is already initialized by the PSP when the x86 cores are released from reset. Therefore they use a different linker script as the rest of the x86 chips in coreboot do. Since there will be support for newer generations than Picasso will be added, move those linker scripts from soc/amd/picasso to soc/amd/common/block/cpu/noncar. TEST=Timeless build of amd/mandolin and amd/gardenia result in identical binaries. Change-Id: Ie60372aa498b6e505708f97213b502c9d0b3534b Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/47828 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/soc/amd/common/block/cpu/Kconfig | 16 ++++++++++++++++ .../block/cpu/noncar}/memlayout.ld | 0 .../block/cpu/noncar}/memlayout_psp_verstage.ld | 2 ++ .../cpu/noncar}/memlayout_transfer_buffer.inc | 0 .../block/cpu/noncar}/memlayout_x86.ld | 0 src/soc/amd/picasso/Kconfig | 5 +---- 6 files changed, 19 insertions(+), 4 deletions(-) rename src/soc/amd/{picasso => common/block/cpu/noncar}/memlayout.ld (100%) rename src/soc/amd/{picasso => common/block/cpu/noncar}/memlayout_psp_verstage.ld (94%) rename src/soc/amd/{picasso => common/block/cpu/noncar}/memlayout_transfer_buffer.inc (100%) rename src/soc/amd/{picasso => common/block/cpu/noncar}/memlayout_x86.ld (100%) diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig index f6756e18f8..826f80bdb5 100644 --- a/src/soc/amd/common/block/cpu/Kconfig +++ b/src/soc/amd/common/block/cpu/Kconfig @@ -11,3 +11,19 @@ config SOC_AMD_COMMON_BLOCK_CAR This is only used for AMD CPU before family 17h. From family 17h on the RAM is already initialized by the PSP before the x86 cores are released from reset. + +config SOC_AMD_COMMON_BLOCK_NONCAR + bool + default n + help + From family 17h on AMD CPUs/APUs don't use cache as RAM (CAR) any + more, since the RAM initialization is already done by the PSP when + the x86 cores are released from reset. + +if SOC_AMD_COMMON_BLOCK_NONCAR + +config MEMLAYOUT_LD_FILE + string + default "src/soc/amd/common/block/cpu/noncar/memlayout.ld" + +endif # SOC_AMD_COMMON_BLOCK_NONCAR diff --git a/src/soc/amd/picasso/memlayout.ld b/src/soc/amd/common/block/cpu/noncar/memlayout.ld similarity index 100% rename from src/soc/amd/picasso/memlayout.ld rename to src/soc/amd/common/block/cpu/noncar/memlayout.ld diff --git a/src/soc/amd/picasso/memlayout_psp_verstage.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_psp_verstage.ld similarity index 94% rename from src/soc/amd/picasso/memlayout_psp_verstage.ld rename to src/soc/amd/common/block/cpu/noncar/memlayout_psp_verstage.ld index ca95cf81bd..aa27bae1d4 100644 --- a/src/soc/amd/picasso/memlayout_psp_verstage.ld +++ b/src/soc/amd/common/block/cpu/noncar/memlayout_psp_verstage.ld @@ -4,6 +4,8 @@ #include #include +/* TODO: Move defines to SoC-specific header file to allow SoC specific values if needed. */ + /* * Start of available space is 0x15000 and this is where the * header for the user app (verstage) must be mapped. diff --git a/src/soc/amd/picasso/memlayout_transfer_buffer.inc b/src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc similarity index 100% rename from src/soc/amd/picasso/memlayout_transfer_buffer.inc rename to src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc diff --git a/src/soc/amd/picasso/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld similarity index 100% rename from src/soc/amd/picasso/memlayout_x86.ld rename to src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 4d7d2a6c1a..6fa36641cd 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -29,6 +29,7 @@ config CPU_SPECIFIC_OPTIONS select TSC_SYNC_LFENCE select UDELAY_TSC select SOC_AMD_COMMON + select SOC_AMD_COMMON_BLOCK_NONCAR select SOC_AMD_COMMON_BLOCK_HAS_ESPI select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_ACPIMMIO @@ -57,10 +58,6 @@ config CPU_SPECIFIC_OPTIONS select SUPPORT_CPU_UCODE_IN_CBFS select ACPI_NO_SMI_GNVS -config MEMLAYOUT_LD_FILE - string - default "src/soc/amd/picasso/memlayout.ld" - config EARLY_RESERVED_DRAM_BASE hex default 0x2000000