superio/winbond/w83627ehg: Depreciate romstage component

Part 1/2: These are actually not necessary if Super I/O support is
properly utilized.

Change-Id: I39b621e582f8d0762276d29492c91dce500f0665
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5870
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Edward O'Callaghan 2014-05-26 04:03:24 +10:00 committed by Kyösti Mälkki
parent 3c3e34d69f
commit 9068788a8f
4 changed files with 2 additions and 45 deletions

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@ -36,6 +36,7 @@
#include "lib/delay.c" #include "lib/delay.c"
#include "cpu/x86/lapic.h" #include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/reset_test.c"
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627ehg/w83627ehg.h> #include <superio/winbond/w83627ehg/w83627ehg.h>
#include "cpu/x86/bist.h" #include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/debug.c"
@ -119,11 +120,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
pnp_enter_ext_func_mode(SERIAL_DEV); pnp_enter_ext_func_mode(SERIAL_DEV);
pnp_write_config(SERIAL_DEV, 0x24, 0); pnp_write_config(SERIAL_DEV, 0x24, 0);
w83627ehg_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
pnp_exit_ext_func_mode(SERIAL_DEV); pnp_exit_ext_func_mode(SERIAL_DEV);
setup_mb_resource_map(); setup_mb_resource_map();
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init(); console_init();
/* Halt if there was a built in self test failure */ /* Halt if there was a built in self test failure */

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@ -19,6 +19,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
## ##
romstage-$(CONFIG_SUPERIO_WINBOND_W83627EHG) += early_init.c
romstage-$(CONFIG_SUPERIO_WINBOND_W83627EHG) += early_serial.c romstage-$(CONFIG_SUPERIO_WINBOND_W83627EHG) += early_serial.c
ramstage-$(CONFIG_SUPERIO_WINBOND_W83627EHG) += superio.c ramstage-$(CONFIG_SUPERIO_WINBOND_W83627EHG) += superio.c

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@ -1,38 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 AMD
* Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/io.h>
#include <device/pnp.h>
#include "w83627ehg.h"
void w83627ehg_disable_dev(device_t dev)
{
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
}
void w83627ehg_enable_dev(device_t dev, u16 iobase)
{
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
pnp_set_enable(dev, 1);
}

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@ -54,11 +54,6 @@
#define W83627EHG_GPIO4 ((2 << 8) | W83627EHG_GPIO_SUSLED_V) #define W83627EHG_GPIO4 ((2 << 8) | W83627EHG_GPIO_SUSLED_V)
#define W83627EHG_GPIO5 ((3 << 8) | W83627EHG_GPIO_SUSLED_V) #define W83627EHG_GPIO5 ((3 << 8) | W83627EHG_GPIO_SUSLED_V)
#if defined(__PRE_RAM__)
void w83627ehg_enable_dev(device_t dev, u16 iobase);
void w83627ehg_disable_dev(device_t dev);
#endif
void pnp_enter_ext_func_mode(device_t dev); void pnp_enter_ext_func_mode(device_t dev);
void pnp_exit_ext_func_mode(device_t dev); void pnp_exit_ext_func_mode(device_t dev);