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mb/google/poppy/variants/nami: Change WiFi wake pin to GPP_E22 

This change updates the WiFi device wake pin to GPP_E22 from WAKE# (to
match the latest schematic changes).

Since WiFi was the only device using WAKE# pin, DSX_EN_WAKE_PIN is
removed from deep_sx_config as well.

BUG=b:72697650
TEST=Verified:
1. Wake-on-wifi works.
2. Device is able to enter G3 without WAKE# pin causing unwanted wakes
from deep S5.

Change-Id: Ibde81f73cca322f9b8b45baf8ee18ae00521467d
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23594
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Furquan Shaikh 2018-02-05 12:08:57 -08:00 committed by Furquan Shaikh
parent 278a5064b4
commit 9076b7bd07
2 changed files with 4 additions and 4 deletions
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4
src/mainboard/google/poppy/variants/nami/devicetree.cb
View File

@ -5,7 +5,7 @@ chip soc/intel/skylake
register "deep_s3_enable_dc" = "1"
register "deep_s5_enable_ac" = "1"
register "deep_s5_enable_dc" = "1"
register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD"
register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD"
# GPE configuration
# Note that GPE events called out in ASL code rely on this
@ -291,7 +291,7 @@ chip soc/intel/skylake
device pci 1c.2 off end # PCI Express Port 3
device pci 1c.3 on
chip drivers/intel/wifi
register "wake" = "GPE0_PCI_EXP"
register "wake" = "GPE0_DW2_22" # Wake pin = GPP_E22
device pci 00.0 on end
end
end # PCI Express Port 4

4
src/mainboard/google/poppy/variants/nami/gpio.c
View File

@ -253,8 +253,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
/* E21 : DDPC_CTRLDATA ==> SOC_DP2_CTRL_DATA */
PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
/* E22 : DDPD_CTRLCLK ==> NC */
PAD_CFG_NC(GPP_E22),
/* E22 : DDPD_CTRLCLK ==> WLAN_PCIE_WAKE# */
PAD_CFG_GPI_ACPI_SCI(GPP_E22, NONE, DEEP, INVERT),
/* E23 : DDPD_CTRLDATA ==> NC */
PAD_CFG_NC(GPP_E23),