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soc/intel/alderlake: Leverage IA common code for range calculations 

Improves code maintainability and potentially reduces redundancy by
using the IA common implementation.

Additionally, drop the unused macros from SoC local.

TEST=Build and boot successful on google/marasov.

Change-Id: I290fea99f04cfc9f18e5f1435ed07de42995869f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80403
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2024-02-08 01:05:02 +05:30
parent 3e4395a8e8
commit 9083f1c501
2 changed files with 4 additions and 126 deletions
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9
src/soc/intel/alderlake/include/soc/systemagent.h
View File

@ -64,15 +64,6 @@ static const struct sa_mmio_descriptor soc_vtd_resources[] = {
#define LT_SECURITY_SIZE (128 * KiB)
#define APIC_SIZE (1 * MiB)
#define MASK_PCIEXBAR_LENGTH 0xE /* bits [3:1] */
#define PCIEXBAR_LENGTH_LSB 1 /* used to shift right */
#define MASK_DSM_LENGTH 0xFF00 /* bits [15:8] */
#define MASK_DSM_LENGTH_LSB 8 /* used to shift right */
#define MASK_GSM_LENGTH 0xC0 /* bits [7:6] */
#define MASK_GSM_LENGTH_LSB 6 /* used to shift right */
#define MASK_DPR_LENGTH 0xFF0 /* bits [11:4] */
#define MASK_DPR_LENGTH_LSB 4 /* used to shift right */
uint64_t get_mmcfg_size(const struct device *dev);
uint64_t get_dsm_size(const struct device *dev);
uint64_t get_gsm_size(const struct device *dev);

121
src/soc/intel/alderlake/systemagent.c
View File

@ -103,13 +103,13 @@ void soc_add_configurable_mmio_resources(struct device *dev, int *resource_cnt)
struct sa_mmio_descriptor cfg_rsrc[6]; /* Increase size when adding more resources */
/* MMCONF */
size = get_mmcfg_size(dev);
size = sa_get_mmcfg_size();
if (size > 0)
set_mmio_resource(&(cfg_rsrc[count++]), CONFIG_ECAM_MMCONF_BASE_ADDRESS,
size, "MMCONF");
/* DSM */
size = get_dsm_size(dev);
size = sa_get_dsm_size();
if (size > 0) {
base = pci_read_config32(dev, BDSM) & 0xFFF00000;
set_mmio_resource(&(cfg_rsrc[count++]), base, size, "DSM");
@ -134,14 +134,14 @@ void soc_add_configurable_mmio_resources(struct device *dev, int *resource_cnt)
}
/* GSM */
size = get_gsm_size(dev);
size = sa_get_gsm_size();
if (size > 0) {
base = sa_get_gsm_base();
set_mmio_resource(&(cfg_rsrc[count++]), base, size, "GSM");
}
/* DPR */
size = get_dpr_size(dev);
size = sa_get_dpr_size();
if (size > 0) {
/* DPR just below TSEG: */
base = tseg_base - size;
@ -208,116 +208,3 @@ uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz)
return 65536;
}
}
uint64_t get_mmcfg_size(const struct device *dev)
{
uint32_t pciexbar_reg;
uint64_t mmcfg_length;
if (!dev) {
printk(BIOS_DEBUG, "%s : device is null\n", __func__);
return 0;
}
pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
if (!(pciexbar_reg & (1 << 0))) {
printk(BIOS_DEBUG, "%s : PCIEXBAR disabled\n", __func__);
return 0;
}
switch ((pciexbar_reg & MASK_PCIEXBAR_LENGTH) >> PCIEXBAR_LENGTH_LSB) {
case PCIEXBAR_LENGTH_4096MB:
mmcfg_length = 4 * ((uint64_t)GiB);
break;
case PCIEXBAR_LENGTH_2048MB:
mmcfg_length = 2 * ((uint64_t)GiB);
break;
case PCIEXBAR_LENGTH_1024MB:
mmcfg_length = 1 * GiB;
break;
case PCIEXBAR_LENGTH_512MB:
mmcfg_length = 512 * MiB;
break;
case PCIEXBAR_LENGTH_256MB:
mmcfg_length = 256 * MiB;
break;
case PCIEXBAR_LENGTH_128MB:
mmcfg_length = 128 * MiB;
break;
case PCIEXBAR_LENGTH_64MB:
mmcfg_length = 64 * MiB;
break;
default:
printk(BIOS_DEBUG, "%s : PCIEXBAR - invalid length (0x%x)\n", __func__,
pciexbar_reg & MASK_PCIEXBAR_LENGTH);
mmcfg_length = 0x0;
break;
}
return mmcfg_length;
}
uint64_t get_dsm_size(const struct device *dev)
{
// - size : B0/D0/F0:R 50h [15:8]
uint32_t reg32 = pci_read_config32(dev, GGC);
uint64_t size;
uint32_t size_field = (reg32 & MASK_DSM_LENGTH) >> MASK_DSM_LENGTH_LSB;
if (size_field <= 0x10) { // 0x0 - 0x10
size = size_field * 32 * MiB;
} else if ((size_field >= 0xF0) && (size_field >= 0xFE)) {
size = ((uint64_t)size_field - 0xEF) * 4 * MiB;
} else {
switch (size_field) {
case 0x20:
size = 1 * GiB;
break;
case 0x30:
size = 1536 * MiB;
break;
case 0x40:
size = 2 * (uint64_t)GiB;
break;
default:
printk(BIOS_DEBUG, "%s : DSM - invalid length (0x%x)\n",
__func__, size_field);
size = 0x0;
break;
}
}
return size;
}
uint64_t get_gsm_size(const struct device *dev)
{
const u32 gsm_size = pci_read_config32(dev, GGC);
uint64_t size;
uint32_t size_field = (gsm_size & MASK_GSM_LENGTH) >> MASK_GSM_LENGTH_LSB;
switch (size_field) {
case 0x0:
size = 0;
break;
case 0x1:
size = 2 * MiB;
break;
case 0x2:
size = 4 * MiB;
break;
case 0x3:
size = 8 * MiB;
break;
default:
size = 0;
break;
}
return size;
}
uint64_t get_dpr_size(const struct device *dev)
{
uint64_t size;
uint32_t dpr_reg = pci_read_config32(dev, DPR);
uint32_t size_field = (dpr_reg & MASK_DPR_LENGTH) >> MASK_DPR_LENGTH_LSB;
size = (uint64_t)size_field * MiB;
return size;
}