GNUBoot/coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

soc/intel/skylake: add CPPC support

Browse source 
ACPI 5.0 defines a method _CPC for "Continuous Performance Control" (CPPC).
Linux has a driver that enables features like speed shift without
consulting ACPI.  Other OSes instead rely on this information and need a
_CPC present. Prior to this change performance in Win10 never exceeds
80% and MSR 0x770 is 0, while with this change (and enabling eist) higher
speeds can be achieved and the MSR value is now 1.

Change-Id: Ib7e0ae13f4b664b51e42f963e53c71f8832be062
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/27673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Matt Delco 2018-07-27 14:17:29 -07:00 committed by Patrick Georgi
parent 9557a34abe
commit 9084c3c31b
2 changed files with 12 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
src/soc/intel/skylake/Makefile.inc
View file

@ -2,6 +2,7 @@ ifeq ($(CONFIG_SOC_INTEL_SKYLAKE),y)
subdirs-y += nhlt
subdirs-y += romstage
subdirs-y += ../../../cpu/intel/common
subdirs-y += ../../../cpu/intel/microcode
subdirs-y += ../../../cpu/intel/turbo
subdirs-y += ../../../cpu/x86/lapic

13
src/soc/intel/skylake/acpi.c
View file

@ -29,6 +29,7 @@
#include <cpu/x86/smm.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/tsc.h>
#include <cpu/intel/common/common.h>
#include <cpu/intel/turbo.h>
#include <ec/google/chromeec/ec.h>
#include <intelblocks/cpulib.h>
@ -520,6 +521,12 @@ void generate_cpu_entries(struct device *device)
printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n",
numcpus, cores_per_package);
if (config->eist_enable && config->speed_shift_enable) {
struct cppc_config cppc_config;
cpu_init_cppc_config(&cppc_config, 2 /* version 2 */);
acpigen_write_CPPC_package(&cppc_config);
}
for (cpu_id = 0; cpu_id < numcpus; cpu_id++) {
for (core_id = 0; core_id < cores_per_package; core_id++) {
if (core_id > 0) {
@ -535,11 +542,13 @@ void generate_cpu_entries(struct device *device)
generate_c_state_entries(is_s0ix_enable,
max_c_state);
if (config->eist_enable)
if (config->eist_enable) {
/* Generate P-state tables */
generate_p_state_entries(core_id,
cores_per_package);
if (config->speed_shift_enable)
acpigen_write_CPPC_method();
}
acpigen_pop_len();
}
}