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mb/google/hades: update TPM IRQ in early gpio table 

TPM IRQ should be A20 not A13. RAM table is correct.

BUG=b:282164589
TEST=able to boot up

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I82a709cc280288d612c65697b8da3c4274d4cd3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75191
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Eric Lai 2023-05-13 15:43:07 +08:00
parent 3707400f80
commit 909829e304
1 changed files with 1 additions and 1 deletions
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2
src/mainboard/google/brya/variants/hades/gpio.c
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@ -383,7 +383,7 @@ static const struct pad_config early_gpio_table[] = {
/* GPP_A12 : [] ==> EN_PPVAR_WWAN */ /* GPP_A12 : [] ==> EN_PPVAR_WWAN */
PAD_CFG_GPO(GPP_A12, 1, DEEP), PAD_CFG_GPO(GPP_A12, 1, DEEP),
/* GPP_A13 : [] ==> GSC_PCH_INT_ODL */ /* GPP_A13 : [] ==> GSC_PCH_INT_ODL */
PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), PAD_CFG_GPI_APIC(GPP_A20, NONE, PLTRST, LEVEL, INVERT),
/* GPP_B4 : [] ==> SSD_PERST_L */ /* GPP_B4 : [] ==> SSD_PERST_L */
PAD_CFG_GPO(GPP_B4, 0, DEEP), PAD_CFG_GPO(GPP_B4, 0, DEEP),
/* GPP_B7 : [] ==> PCH_I2C_TPM_SDA */ /* GPP_B7 : [] ==> PCH_I2C_TPM_SDA */