mainboard/msi/ms7d25: Add early support for MSI PRO Z690-A DDR4 WIFI

Initial mainboard code MSI PRO Z690-A DDR4 WIFI. The platform boots up
up to romstage where it returns from FSP memory init with an error.

What works:
- open-source CAR setup
- NCT6687D serial port with TX pin exposed on JBD1 header
- SMBus reading SPD from all 4 DIMMs

This board will serve as a reference board for enabling Alder Lake-S
support in coreboot. More code and functionalities will be added in
subsequent patches as src/soc/alderlake code will be improved for
PCH-S.

TEST=Extract the microcode from vendor firmware and include it in the
build. The platform should print the console on the serial port even
without FSP blob.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I5df69822dbb3ff79e087408a0693de37df2142e8
Signed-off-by: Igor Bagnucki <igor.bagnucki@3mdeb.com>
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>

configs/config.msi_ms7d25

@@ -0,0 +1,16 @@
+CONFIG_VENDOR_MSI=y
+CONFIG_CBFS_SIZE=0x1000000
+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
+CONFIG_TIANOCORE_BOOT_TIMEOUT=3
+CONFIG_BOARD_MSI_Z690_A_PRO_WIFI_DDR4=y
+# CONFIG_SMMSTORE is not set
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
+CONFIG_POST_DEVICE_PCI_PCIE=y
+CONFIG_POST_IO_PORT=0x80
+CONFIG_PAYLOAD_TIANOCORE=y
+CONFIG_TIANOCORE_REPOSITORY="https://github.com/Dasharo/edk2.git"
+CONFIG_TIANOCORE_TAG_OR_REV="origin/dasharo"
+CONFIG_TIANOCORE_CBMEM_LOGGING=y
+CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC=y
+CONFIG_TIANOCORE_SD_MMC_TIMEOUT=1000
+CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y

src/mainboard/msi/ms7d25/Kconfig

@@ -0,0 +1,45 @@
+config BOARD_MSI_Z690_A_PRO_WIFI_DDR4
+	select BOARD_MSI_MS7D25
+
+config BOARD_MSI_MS7D25
+	def_bool n
+	select SOC_INTEL_ALDERLAKE_PCH_S
+	select BOARD_ROMSIZE_KB_32768
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SUPERIO_NUVOTON_NCT6687D
+	select DRIVERS_UART_8250IO
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+
+if BOARD_MSI_MS7D25
+
+config MAINBOARD_DIR
+	default "msi/ms7d25"
+
+config MAINBOARD_PART_NUMBER
+	default "PRO Z690-A WIFI DDR4(MS-7D25)" if BOARD_MSI_Z690_A_PRO_WIFI_DDR4
+
+config MAINBOARD_VENDOR
+	string
+	default "Micro-Star International Co., Ltd."
+
+config DIMM_SPD_SIZE
+	default 512
+
+config UART_FOR_CONSOLE
+	int
+	default 0
+
+config USE_PM_ACPI_TIMER
+	bool
+	default n
+
+config USE_LEGACY_8254_TIMER
+	bool
+	default n
+
+config CBFS_SIZE
+	hex
+	default 0x1000000
+
+endif

src/mainboard/msi/ms7d25/Kconfig.name

@@ -0,0 +1,2 @@
+config BOARD_MSI_Z690_A_PRO_WIFI_DDR4
+	bool "PRO Z690-A WIFI DDR4"

src/mainboard/msi/ms7d25/Makefile.inc

@@ -0,0 +1,7 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c
+
+romstage-y += romstage_fsp_params.c
+
+ramstage-y += mainboard.c

src/mainboard/msi/ms7d25/board_info.txt

@@ -0,0 +1,7 @@
+Category: desktop
+Board URL: https://www.msi.com/Motherboard/PRO-Z690-A-WIFI-DDR4
+ROM IC: MX25U25673G
+ROM package: WSON-8
+ROM socketed: no
+Flashrom support: yes
+Release year: 2021

src/mainboard/msi/ms7d25/bootblock.c

@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pnp_ops.h>
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct6687d/nct6687d.h>
+
+#define SERIAL_DEV PNP_DEV(0x4e, NCT6687D_SP1)
+
+void bootblock_mainboard_early_init(void)
+{
+	/* Replicate vendor settings for multi-function pins in global config LDN */
+	nuvoton_pnp_enter_conf_state(SERIAL_DEV);
+	pnp_write_config(SERIAL_DEV, 0x15, 0xaa);
+	pnp_write_config(SERIAL_DEV, 0x1a, 0x02);
+	pnp_write_config(SERIAL_DEV, 0x1b, 0x02);
+	pnp_write_config(SERIAL_DEV, 0x1d, 0x00);
+	pnp_write_config(SERIAL_DEV, 0x1e, 0xaa);
+	pnp_write_config(SERIAL_DEV, 0x1f, 0xb2);
+	pnp_write_config(SERIAL_DEV, 0x22, 0xbd);
+	pnp_write_config(SERIAL_DEV, 0x23, 0xdf);
+	pnp_write_config(SERIAL_DEV, 0x24, 0x39);
+	pnp_write_config(SERIAL_DEV, 0x25, 0xfe);
+	pnp_write_config(SERIAL_DEV, 0x26, 0x40);
+	pnp_write_config(SERIAL_DEV, 0x27, 0x77);
+	pnp_write_config(SERIAL_DEV, 0x28, 0x00);
+	pnp_write_config(SERIAL_DEV, 0x29, 0xfb);
+	pnp_write_config(SERIAL_DEV, 0x2a, 0x80);
+	pnp_write_config(SERIAL_DEV, 0x2b, 0x20);
+	pnp_write_config(SERIAL_DEV, 0x2c, 0x8a);
+	pnp_write_config(SERIAL_DEV, 0x2d, 0xaa);
+	nuvoton_pnp_exit_conf_state(SERIAL_DEV);
+
+	if (CONFIG(CONSOLE_SERIAL))
+		nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}

src/mainboard/msi/ms7d25/devicetree.cb

@@ -0,0 +1,28 @@
+chip soc/intel/alderlake
+	device domain 0 on
+		device ref igpu on end
+		device ref crashlog off end
+		device ref xhci on end
+		device ref heci1 on end
+		device ref heci2 off end
+		device ref ide_r off end
+		device ref kt off end
+		device ref heci3 off end
+		device ref heci4 off end
+		device ref sata on end
+		device ref pcie_rp1 on end
+		device ref pcie_rp2 on end
+		device ref pcie_rp3 on end
+		device ref pcie_rp4 on end
+		device ref pcie_rp5 on end
+		device ref pcie_rp6 on end
+		device ref pcie_rp7 on end
+		device ref pcie_rp8 on end
+		device ref pcie_rp9 on end
+		device ref pcie_rp10 on end
+		device ref pcie_rp11 on end
+		device ref p2sb on end
+		device ref hda on end
+		device ref smbus on end
+	end
+end

src/mainboard/msi/ms7d25/dsdt.asl

@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include <soc/intel/common/block/acpi/acpi/platform.asl>
+
+	/* global NVS and variables */
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0) {
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/alderlake/acpi/southbridge.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+}

src/mainboard/msi/ms7d25/hda_verb.c

@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek ALC897 */
+	0x10ec0897, /* Vendor ID */
+	0x14629d25, /* Subsystem ID */
+	15, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x14629d25),
+	AZALIA_PIN_CFG(0, 0x11, 0x4037d540),
+	AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x14, 0x01014010),
+	AZALIA_PIN_CFG(0, 0x15, 0x01011012),
+	AZALIA_PIN_CFG(0, 0x16, 0x01016011),
+	AZALIA_PIN_CFG(0, 0x17, 0x01012014),
+	AZALIA_PIN_CFG(0, 0x18, 0x01a19030),
+	AZALIA_PIN_CFG(0, 0x19, 0x02a19040),
+	AZALIA_PIN_CFG(0, 0x1a, 0x0181303f),
+	AZALIA_PIN_CFG(0, 0x1b, 0x02214020),
+	AZALIA_PIN_CFG(0, 0x1c, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x402af66b),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
+
+	/* Alderlake HDMI */
+	0x80862815, /* Vendor ID */
+	0x80860101, /* Subsystem ID */
+	2, /* Number of entries */
+	AZALIA_SUBVENDOR(2, 0x80860101),
+	AZALIA_PIN_CFG(2, 0x04, 0x18560010),
+};
+
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;

src/mainboard/msi/ms7d25/mainboard.c

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+
+static void mainboard_init(void *chip_info)
+{
+
+}
+
+static void mainboard_enable(struct device *dev)
+{
+
+}
+
+struct chip_operations mainboard_ops = {
+	.init = mainboard_init,
+	.enable_dev = mainboard_enable,
+};

src/mainboard/msi/ms7d25/romstage_fsp_params.c

@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <assert.h>
+#include <console/console.h>
+#include <fsp/api.h>
+#include <soc/romstage.h>
+#include <soc/meminit.h>
+
+static const struct mb_cfg ddr4_mem_config = {
+	.type = MEM_TYPE_DDR4,
+
+	.rcomp = {
+		/* Baseboard uses only 100ohm Rcomp resistor FIXME */
+		.resistor = 100,
+
+		/* Baseboard Rcomp target values FIXME */
+		.targets = { 50, 20, 25, 25, 25 },
+	},
+
+	.UserBd = BOARD_TYPE_DESKTOP_2DPC, /* FIXME */
+
+	.ddr_config = {
+		.dq_pins_interleaved = false, /* FIXME */
+	},
+};
+
+static const struct mem_spd dimm_module_spd_info = {
+	.topo = MEM_TOPO_DIMM_MODULE,
+	.smbus = {
+		[0] = {
+			.addr_dimm[0] = 0x50,
+			.addr_dimm[1] = 0x51,
+		},
+		[1] = {
+			.addr_dimm[0] = 0x52,
+			.addr_dimm[1] = 0x53,
+		},
+	},
+};
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+	memcfg_init(memupd, &ddr4_mem_config, &dimm_module_spd_info, false);
+}