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soc/amd/common/block/spi: introduce SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST 

Add a new Kconfig option to enable or disable the 4 DWORD burst support
of the SPI controller and use this setting to determine if the
corresponding feature bit in SPI100_HOST_PREF_CONFIG will be set or
cleared. Since fch_spi_disable_4dw_burst can now enable or disable the
feature, rename it to fch_spi_configure_4dw_burst. On Stoneyridge the
SPI_RD4DW_EN_HOST bit needs to be cleared (see the Rd4dw_en_host bit
definition in the SPIx2C SPI100 Host Prefetch Config register in the
public BKDG #55072 Rev 3.09), so add a SoC dependency to the Kconfig
option.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id754fa8d5f9554ed25cf9f3341bfdd1968693788
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit is contained in:
Felix Held 2021-08-04 22:22:46 +02:00 committed by Martin Roth
parent c2cf3946c9
commit 90ac882a32
2 changed files with 14 additions and 3 deletions
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6
src/soc/amd/common/block/spi/Kconfig
View File

@ -8,6 +8,12 @@ config SOC_AMD_COMMON_BLOCK_SPI
config SOC_AMD_COMMON_BLOCK_SPI_DEBUG
bool
config SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST
bool
depends on !SOC_AMD_STONEYRIDGE
help
Select this option to keep the 4 DWORD burst support enabled.
config EFS_SPI_READ_MODE
int
range 0 7

11
src/soc/amd/common/block/spi/fch_spi.c
View File

@ -15,11 +15,16 @@ static void fch_spi_set_spi100(int norm, int fast, int alt, int tpm)
spi_write16(SPI100_ENABLE, SPI_USE_SPI100);
}
static void fch_spi_disable_4dw_burst(void)
static void fch_spi_configure_4dw_burst(void)
{
uint16_t val = spi_read16(SPI100_HOST_PREF_CONFIG);
spi_write16(SPI100_HOST_PREF_CONFIG, val & ~SPI_RD4DW_EN_HOST);
if (CONFIG(SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST))
val |= SPI_RD4DW_EN_HOST;
else
val &= ~SPI_RD4DW_EN_HOST;
spi_write16(SPI100_HOST_PREF_CONFIG, val);
}
static void fch_spi_set_read_mode(u32 mode)
@ -61,6 +66,6 @@ void fch_spi_early_init(void)
{
lpc_enable_spi_rom(SPI_ROM_ENABLE);
lpc_enable_spi_prefetch();
fch_spi_disable_4dw_burst();
fch_spi_configure_4dw_burst();
fch_spi_config_modes();
}