armv7: Clean up the mmu setup a bit
The previous incarnation did not use all of mmu_setup, which meant we did not carefully disable things before (possibly) changing them. This code is tested and works, and it's a bit of a simplification. Change-Id: I0560f9b8e25f31cd90e34304d6ec987fc5c87699 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2204 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
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@ -239,10 +239,10 @@ uint rd_dc_cst (void);
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void wr_dc_cst (uint);
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void wr_dc_adr (uint);
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int icache_status (void);
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void icache_enable (void);
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void icache_enable (unsigned long start, unsigned long size);
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void icache_disable(void);
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int dcache_status (void);
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void dcache_enable (void);
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void dcache_enable (unsigned long start, unsigned long size);
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void dcache_disable(void);
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void mmu_disable(void);
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ulong get_endaddr (void);
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@ -106,7 +106,7 @@ void mmu_set_region_dcache(unsigned long start, int size,
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*/
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void mmu_page_table_flush(unsigned long start, unsigned long stop);
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void dram_bank_mmu_setup(unsigned long start, unsigned long size);
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void mmu_setup(unsigned long start, unsigned long size);
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void arm_init_before_mmu(void);
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@ -91,32 +91,13 @@ void mmu_set_region_dcache(unsigned long start, int size, enum dcache_option opt
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mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]);
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}
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#if 0
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static inline void dram_bank_mmu_setup(int bank)
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{
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// bd_t *bd = gd->bd;
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int i;
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debug("%s: bank: %d\n", __func__, bank);
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for (i = bd->bi_dram[bank].start >> 20;
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i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20;
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i++) {
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#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
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set_section_dcache(i, DCACHE_WRITETHROUGH);
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#else
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set_section_dcache(i, DCACHE_WRITEBACK);
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#endif
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}
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}
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#endif
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/**
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* dram_bank_mmu_set - set up the data cache policy for a given dram bank
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*
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* @start: virtual address start of bank
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* @size: size of bank (in bytes)
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*/
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inline void dram_bank_mmu_setup(unsigned long start, unsigned long size)
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static inline void dram_bank_mmu_setup(unsigned long start, unsigned long size)
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{
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int i;
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@ -133,27 +114,17 @@ inline void dram_bank_mmu_setup(unsigned long start, unsigned long size)
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}
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/* to activate the MMU we need to set up virtual memory: use 1M areas */
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static inline void mmu_setup(void)
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inline void mmu_setup(unsigned long start, unsigned long size)
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{
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int i;
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u32 reg;
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arm_init_before_mmu();
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/* Set up an identity-mapping for all 4GB, rw for everyone */
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for (i = 0; i < 4096; i++)
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set_section_dcache(i, DCACHE_OFF);
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/* FIXME(dhendrix): u-boot's global data struct was used here... */
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#if 0
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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dram_bank_mmu_setup(i);
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}
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#endif
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#if 0
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/* comes from board's romstage.c, since we need to know which
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ranges to setup */
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mainboard_setup_mmu();
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#endif
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dram_bank_mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB << 20);
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/* Copy the page table address to cp15 */
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@ -174,13 +145,13 @@ static int mmu_enabled(void)
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}
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/* cache_bit must be either CR_I or CR_C */
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static void cache_enable(uint32_t cache_bit)
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static void cache_enable(unsigned long start, unsigned long size, uint32_t cache_bit)
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{
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uint32_t reg;
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/* The data cache is not active unless the mmu is enabled too */
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if ((cache_bit == CR_C) && !mmu_enabled())
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mmu_setup();
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mmu_setup(start, size);
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reg = get_cr(); /* get control reg. */
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cp_delay();
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set_cr(reg | cache_bit);
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@ -216,9 +187,9 @@ static void cache_disable(uint32_t cache_bit)
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set_cr(reg & ~cache_bit);
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}
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void icache_enable(void)
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void icache_enable(unsigned long start, unsigned long size)
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{
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cache_enable(CR_I);
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cache_enable(start, size, CR_I);
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}
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void icache_disable(void)
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@ -231,9 +202,9 @@ int icache_status(void)
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return (get_cr() & CR_I) != 0;
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}
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void dcache_enable(void)
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void dcache_enable(unsigned long start, unsigned long size)
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{
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cache_enable(CR_C);
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cache_enable(start, size, CR_C);
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}
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void dcache_disable(void)
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@ -39,7 +39,8 @@ enum l2_cache_params {
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void enable_caches(void)
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{
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/* Enable D-cache. I-cache is already enabled in start.S */
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dcache_enable();
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/* can't use it anyway -- it has dependencies we have to fix. */
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//dcache_enable();
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}
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#endif
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@ -37,11 +37,6 @@
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#endif
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#include <console/console.h>
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static void mmu_setup(void)
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{
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dram_bank_mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB * 1024);
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}
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void main(void);
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void main(void)
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{
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@ -54,5 +49,5 @@ void main(void)
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printk(BIOS_INFO, "hello from romstage\n");
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// *pshold &= ~0x100; /* shut down */
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mmu_setup();
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mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB * 1024);
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}
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