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src/cpu: Remove unnecessary whitespace 

Change-Id: I0903b7ca9eada4beacfcdbcacddec23c3515651e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16850
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Elyes HAOUAS 2016-10-02 10:23:01 +02:00 committed by Martin Roth
parent 035df005c5
commit 90ba189744
8 changed files with 30 additions and 30 deletions
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6
src/cpu/allwinner/a10/raminit.c
View File

@ -205,7 +205,7 @@ static int dramc_scan_readpipe(void)
setbits_le32(&dram->ccr, DRAM_CCR_DATA_TRAINING);
/* check whether data training process has completed */
while (read32(&dram->ccr) & DRAM_CCR_DATA_TRAINING) ;
while (read32(&dram->ccr) & DRAM_CCR_DATA_TRAINING);
/* check data training result */
reg32 = read32(&dram->csr);
@ -408,7 +408,7 @@ unsigned long dramc_init(struct dram_para *para)
udelay(1);
while (read32(&dram->ccr) & DRAM_CCR_INIT) ;
while (read32(&dram->ccr) & DRAM_CCR_INIT);
mctl_enable_dllx(para->tpr3);
@ -452,7 +452,7 @@ unsigned long dramc_init(struct dram_para *para)
/* reset external DRAM */
setbits_le32(&dram->ccr, DRAM_CCR_INIT);
while (read32(&dram->ccr) & DRAM_CCR_INIT) ;
while (read32(&dram->ccr) & DRAM_CCR_INIT);
/* scan read pipe value */
mctl_itm_enable();

4
src/cpu/allwinner/a10/uart.c
View File

@ -82,7 +82,7 @@ static int rx_fifo_empty(struct a10_uart *uart)
*/
static u8 a10_uart_rx_blocking(struct a10_uart *uart)
{
while (rx_fifo_empty(uart)) ;
while (rx_fifo_empty(uart));
return read32(&uart->rbr);
}
@ -94,7 +94,7 @@ static u8 a10_uart_rx_blocking(struct a10_uart *uart)
*/
static void a10_uart_tx_blocking(struct a10_uart *uart, u8 data)
{
while (tx_fifo_full(uart)) ;
while (tx_fifo_full(uart));
return write32(&uart->thr, data);
}

30
src/cpu/amd/family_10h-family_15h/fidvid.c
View File

@ -151,7 +151,7 @@ static void applyBoostFIDOffset(pci_devfn_t dev, uint32_t nodeid)
u32 cpuFid = msr.lo & PS_CPU_FID_MASK;
cpuFid = cpuFid + asymetricBoostThisCore;
msr.lo &= ~PS_CPU_FID_MASK;
msr.lo |= cpuFid ;
msr.lo |= cpuFid;
wrmsr(PS_REG_BASE , msr);
} else if (is_fam15h()) {
uint32_t dword = pci_read_config32(NODE_PCI(nodeid, 4), 0x15c);
@ -192,7 +192,7 @@ static u8 setPStateMaxVal(pci_devfn_t dev)
for (i = 0; i < NM_PS_REG; i++) {
msr_t msr = rdmsr(PS_REG_BASE + i);
if (msr.hi & PS_IDD_VALUE_MASK) {
msr.hi |= PS_EN_MASK ;
msr.hi |= PS_EN_MASK;
wrmsr(PS_REG_BASE + i, msr);
}
if (msr.hi & PS_EN_MASK) {
@ -387,9 +387,9 @@ static u32 nb_clk_did(uint8_t node, uint64_t cpuRev, uint8_t procPkg) {
package S1g3 from S1g4 */
if ((cpuRev & AMD_DA_C2) && (procPkg & AMD_PKGTYPE_S1gX)
&& link0isGen3) {
return 5 ; /* divide clk by 128*/
return 5; /* divide clk by 128*/
} else {
return 4 ; /* divide clk by 16 */
return 4; /* divide clk by 16 */
}
}
@ -411,7 +411,7 @@ static u32 power_up_down(int node, u8 procPkg) {
uint32_t dispRefModeEn = (pci_read_config32(NODE_PCI(node,0),0x68) >> 24) & 1;
uint32_t isocEn = 0;
int j;
for (j=0 ; (j<4) && (!isocEn) ; j++ ) {
for (j=0; (j<4) && (!isocEn); j++ ) {
u8 offset;
if (AMD_CpuFindCapability(node, j, &offset)) {
isocEn = (pci_read_config32(NODE_PCI(node,0),offset+4) >>12) & 1;
@ -422,7 +422,7 @@ static u32 power_up_down(int node, u8 procPkg) {
/* Family 15h always uses 100ns for multilink processors */
dword |= PW_STP_UP100 | PW_STP_DN100;
} else if (dispRefModeEn || isocEn) {
dword |= PW_STP_UP50 | PW_STP_DN50 ;
dword |= PW_STP_UP50 | PW_STP_DN50;
} else {
/* get number of cores for PowerStepUp & PowerStepDown in server
* 1 core - 400nS - 0000b
@ -487,7 +487,7 @@ static void config_power_ctrl_misc_reg(pci_devfn_t dev, uint64_t cpuRev,
/* PllLockTime and PsiVidEn set in ruleset in defaults.h */
if (dword & PVI_MODE) { /* PVI */
/* set slamVidMode to 0 for PVI */
dword &= VID_SLAM_OFF ;
dword &= VID_SLAM_OFF;
} else { /* SVI */
/* set slamVidMode to 1 for SVI */
dword |= VID_SLAM_ON;
@ -500,7 +500,7 @@ static void config_power_ctrl_misc_reg(pci_devfn_t dev, uint64_t cpuRev,
if ((procPkg == AMD_PKGTYPE_G34) || (procPkg == AMD_PKGTYPE_C32) ) {
dword |= BP_INS_TRI_EN_ON ;
dword |= BP_INS_TRI_EN_ON;
}
/* TODO: look into C1E state and F3xA0[IdleExitEn]*/
@ -615,7 +615,7 @@ static void prep_fid_change(void)
for (i = 0; i < nodes; i++) {
printk(BIOS_DEBUG, "Prep FID/VID Node:%02x\n", i);
dev = NODE_PCI(i, 3);
uint64_t cpuRev = mctGetLogicalCPUID(0xFF) ;
uint64_t cpuRev = mctGetLogicalCPUID(0xFF);
u8 procPkg = mctGetProcessorPackageType();
setVSRamp(dev);
@ -647,7 +647,7 @@ static void waitCurrentPstate(u32 target_pstate) {
msr_t initial_msr = rdmsr(TSC_MSR);
msr_t pstate_msr = rdmsr(CUR_PSTATE_MSR);
msr_t tsc_msr;
u8 timedout ;
u8 timedout;
/* paranoia ? I fear when we run fixPsNbVidBeforeWR we can enter a
* P1 that is a copy of P0, therefore has the same NB DID but the
@ -660,7 +660,7 @@ static void waitCurrentPstate(u32 target_pstate) {
WAIT_PSTATE_TIMEOUT*2 : WAIT_PSTATE_TIMEOUT;
msr_t timeout;
timeout.lo = initial_msr.lo + corrected_timeout ;
timeout.lo = initial_msr.lo + corrected_timeout;
timeout.hi = initial_msr.hi;
if ( (((u32)0xffffffff) - initial_msr.lo) < corrected_timeout ) {
timeout.hi++;
@ -672,7 +672,7 @@ static void waitCurrentPstate(u32 target_pstate) {
tsc_msr = rdmsr(TSC_MSR);
timedout = (tsc_msr.hi > timeout.hi)
|| ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo ));
} while ( (pstate_msr.lo != target_pstate) && (! timedout) ) ;
} while ( (pstate_msr.lo != target_pstate) && (! timedout) );
if (pstate_msr.lo != target_pstate) {
msr_t limit_msr = rdmsr(0xc0010061);
@ -681,7 +681,7 @@ static void waitCurrentPstate(u32 target_pstate) {
do { // should we just go on instead ?
pstate_msr = rdmsr(CUR_PSTATE_MSR);
} while ( pstate_msr.lo != target_pstate ) ;
} while ( pstate_msr.lo != target_pstate );
}
}
@ -838,8 +838,8 @@ static u32 init_fidvid_core(u32 nodeid, u32 coreid)
reg1fc = pci_read_config32(dev, 0x1FC);
if (nb_cof_vid_update) {
vid_max = (reg1fc & SINGLE_PLANE_NB_VID_MASK ) >> SINGLE_PLANE_NB_VID_SHIFT ;
fid_max = (reg1fc & SINGLE_PLANE_NB_FID_MASK ) >> SINGLE_PLANE_NB_FID_SHIFT ;
vid_max = (reg1fc & SINGLE_PLANE_NB_VID_MASK ) >> SINGLE_PLANE_NB_VID_SHIFT;
fid_max = (reg1fc & SINGLE_PLANE_NB_FID_MASK ) >> SINGLE_PLANE_NB_FID_SHIFT;
if (!pvimode) { /* SVI, dual power plane */
vid_max = vid_max - ((reg1fc & DUAL_PLANE_NB_VID_OFF_MASK ) >> DUAL_PLANE_NB_VID_SHIFT );

4
src/cpu/amd/family_10h-family_15h/powernow_acpi.c
View File

@ -227,8 +227,8 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
/*
* Based on the CPU socket type,cmp_cap and pwr_lmt , get the power limit.
* socket_type : 0x10 SocketF; 0x11 AM2/ASB1 ; 0x12 S1G1
* cmp_cap : 0x0 SingleCore ; 0x1 DualCore ; 0x2 TripleCore ; 0x3 QuadCore ; 0x4 QuintupleCore ; 0x5 HexCore
* socket_type : 0x10 SocketF; 0x11 AM2/ASB1; 0x12 S1G1
* cmp_cap : 0x0 SingleCore; 0x1 DualCore; 0x2 TripleCore; 0x3 QuadCore; 0x4 QuintupleCore; 0x5 HexCore
*/
printk(BIOS_INFO, "Pstates algorithm ...\n");
fam15h = !!(mctGetLogicalCPUID(0) & AMD_FAM15_ALL);

4
src/cpu/amd/model_fxx/powernow_acpi.c
View File

@ -156,8 +156,8 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
/*
* Based on the CPU socket type,cmp_cap and pwr_lmt , get the power limit.
* socket_type : 0x10 SocketF; 0x11 AM2/ASB1 ; 0x12 S1G1
* cmp_cap : 0x0 SingleCore ; 0x1 DualCore
* socket_type : 0x10 SocketF; 0x11 AM2/ASB1; 0x12 S1G1
* cmp_cap : 0x0 SingleCore; 0x1 DualCore
*/
printk(BIOS_INFO, "Pstates Algorithm ...\n");

2
src/cpu/via/nano/update_ucode.c
View File

@ -62,7 +62,7 @@ static ucode_validity nano_ucode_is_valid(const nano_ucode_header *ucode)
int i;
u32 check = 0;
u32 *raw = (void*) ucode;
for (i = 0 ; i < ((ucode->total_size) >> 2); i++) {
for (i = 0; i < ((ucode->total_size) >> 2); i++) {
check += raw[i];
}
if (check != 0)

2
src/cpu/x86/16bit/reset16.ld
View File

@ -10,7 +10,7 @@ SECTIONS {
. = _ROMTOP;
.reset . : {
*(.reset);
. = 15 ;
. = 15;
BYTE(0x00);
}
}

8
src/cpu/x86/lapic/lapic_cpu_init.c
View File

@ -307,7 +307,7 @@ int start_cpu(struct device *cpu)
if (result) {
result = 0;
/* Wait 1s or until the new CPU calls in */
for (count = 0; count < 100000 ; count++) {
for (count = 0; count < 100000; count++) {
if (secondary_stack == 0) {
result = 1;
break;
@ -436,7 +436,7 @@ static void start_other_cpus(struct bus *cpu_bus, struct device *bsp_cpu)
struct device *cpu;
/* Loop through the cpus once getting them started */
for (cpu = cpu_bus->children; cpu ; cpu = cpu->sibling) {
for (cpu = cpu_bus->children; cpu; cpu = cpu->sibling) {
if (cpu->path.type != DEVICE_PATH_APIC) {
continue;
}
@ -471,7 +471,7 @@ static void smm_other_cpus(struct bus *cpu_bus, device_t bsp_cpu)
/* Loop through the cpus once to let them run through SMM relocator */
for (cpu = cpu_bus->children; cpu ; cpu = cpu->sibling) {
for (cpu = cpu_bus->children; cpu; cpu = cpu->sibling) {
if (cpu->path.type != DEVICE_PATH_APIC) {
continue;
}
@ -493,7 +493,7 @@ static void smm_other_cpus(struct bus *cpu_bus, device_t bsp_cpu)
}
/* FIXME: endless loop */
while (atomic_read(&active_cpus) != pre_count) ;
while (atomic_read(&active_cpus) != pre_count);
}
}