slippy: Update interrupt routing
The SerialIO devices have specific requirements for PCI
interrupt mode to use PIRQ{E,F,G,H} that are not being met.
D21:F0 uses PIRQE, which must not be shared with other PCH
D21:F1-F6 share PIRQF, which must not be shared with other PCH
D23:F0 uses PIRQH, which must not be shared with other PCH
- Fix D20IR -> D20IP typo
- Remove D25/EHCI2 as it does not exist
- Reorder other interrupts to clear PIRQE/PIRQF/PIRQH
Check device interrupts in the kernel
0: IO-APIC-edge timer
1: IO-APIC-edge i8042
8: IO-APIC-edge rtc0
9: IO-APIC-fasteoi acpi
16: IO-APIC-fasteoi ath9k
18: IO-APIC-fasteoi i801_smbus
19: IO-APIC-fasteoi ehci_hcd:usb1
21: IO-APIC-fasteoi i2c-designware-pci--1, i2c-designware-pci--1
40: PCI-MSI-edge PCIe PME
41: PCI-MSI-edge i915
42: PCI-MSI-edge ahci
43: PCI-MSI-edge xhci_hcd
44: PCI-MSI-edge snd_hda_intel
Change-Id: Id4c08d11d2860f270c6387138acdc7d3d83a85b5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56028
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4176
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Duncan Laurie
Alexandru Gagniuc
parent
a54adc1bc7
commit
90bfbfa9ba
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@ -29,26 +29,26 @@ Method(_PRT)
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// High Definition Audio 0:1b.0
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Package() { 0x001bffff, 0, 0, 22 },
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// PCIe Root Ports 0:1c.x
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Package() { 0x001cffff, 0, 0, 17 },
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Package() { 0x001cffff, 1, 0, 18 },
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Package() { 0x001cffff, 2, 0, 19 },
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Package() { 0x001cffff, 3, 0, 20 },
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Package() { 0x001cffff, 0, 0, 16 },
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Package() { 0x001cffff, 1, 0, 17 },
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Package() { 0x001cffff, 2, 0, 18 },
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Package() { 0x001cffff, 3, 0, 19 },
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// EHCI 0:1d.0
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Package() { 0x001dffff, 0, 0, 19 },
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// XHCI 0:14.0
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Package() { 0x0014ffff, 0, 0, 16 },
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Package() { 0x0014ffff, 0, 0, 18 },
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// LPC devices 0:1f.0
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Package() { 0x001fffff, 0, 0, 21 },
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Package() { 0x001fffff, 1, 0, 22 },
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Package() { 0x001fffff, 2, 0, 23 },
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Package() { 0x001fffff, 1, 0, 18 },
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Package() { 0x001fffff, 2, 0, 17 },
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Package() { 0x001fffff, 3, 0, 16 },
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// Serial IO 0:15.0
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Package() { 0x0015ffff, 0, 0, 16 },
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Package() { 0x0015ffff, 1, 0, 17 },
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Package() { 0x0015ffff, 2, 0, 18 },
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Package() { 0x0015ffff, 3, 0, 19 },
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Package() { 0x0015ffff, 0, 0, 20 },
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Package() { 0x0015ffff, 1, 0, 21 },
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Package() { 0x0015ffff, 2, 0, 21 },
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Package() { 0x0015ffff, 3, 0, 21 },
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// SDIO 0:17.0
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Package() { 0x0017ffff, 0, 0, 16 },
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Package() { 0x0017ffff, 0, 0, 23 },
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})
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} Else {
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Return (Package() {
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@ -57,19 +57,26 @@ Method(_PRT)
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// High Definition Audio 0:1b.0
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Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
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// PCIe Root Ports 0:1c.x
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Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
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Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
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Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
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Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 },
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// EHCI #1 0:1d.0
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Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
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Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
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Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
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// EHCI 0:1d.0
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Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
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// EHCI #2 0:1a.0
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Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
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// XHCI 0:14.0
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Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
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// LPC device 0:1f.0
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Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
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Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 },
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Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 },
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Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
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Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
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Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
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Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
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// Serial IO 0:15.0
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Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
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Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
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Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 },
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Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 },
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// SDIO 0:17.0
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Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
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})
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}
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}
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@ -35,13 +35,12 @@ const struct rcba_config_instruction rcba_config[] = {
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/*
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* GFX INTA -> PIRQA (MSI)
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* D28IP_P1IP WLAN INTA -> PIRQB
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* D28IP_P4IP ETH0 INTB -> PIRQC
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* D29IP_E1P EHCI1 INTA -> PIRQD
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* D20IP_XHCI XHCI INTA -> PIRQA
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* D28IP_P1IP PCIE INTA -> PIRQA
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* D29IP_E1P EHCI INTA -> PIRQD
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* D20IP_XHCI XHCI INTA -> PIRQC (MSI)
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* D31IP_SIP SATA INTA -> PIRQF (MSI)
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* D31IP_SMIP SMBUS INTB -> PIRQG
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* D31IP_TTIP THRT INTC -> PIRQH
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* D31IP_TTIP THRT INTC -> PIRQA
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* D27IP_ZIP HDA INTA -> PIRQG (MSI)
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*/
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@ -53,21 +52,18 @@ const struct rcba_config_instruction rcba_config[] = {
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(INTB << D28IP_P4IP)),
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RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)),
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RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)),
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RCBA_SET_REG_32(D25IP, (NOINT << D25IP_LIP)),
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RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)),
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RCBA_SET_REG_32(D20IR, (INTA << D20IP_XHCI)),
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RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)),
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/* Device interrupt route registers */
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RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQF, PIRQG, PIRQH, PIRQA)),
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RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG)),
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RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE)),
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RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQH, PIRQA, PIRQB)),
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RCBA_SET_REG_32(D26IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)),
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RCBA_SET_REG_32(D25IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),
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RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),
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RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),
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RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),
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RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQA, 0, 0, 0)),
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RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */
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RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */
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RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */
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RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */
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RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */
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RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */
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RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */
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RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */
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/* Disable unused devices (board specific) */
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RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS),
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