Add initial inteltool support for Intel 440BX/440LX and 82371AB/EB/MB.
Signed-off-by: Maciej Pijanka <maciej.pijanka@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4694 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Maciej Pijanka
Uwe Hermann
parent
2583dd2095
commit
90d17407d8
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@ -131,6 +131,9 @@ int print_gpios(struct pci_dev *sb)
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gpio_registers = ich0_gpio_registers;
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size = ARRAY_SIZE(ich0_gpio_registers);
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break;
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case PCI_DEVICE_ID_INTEL_82371XX:
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printf("This southbridge has GPIOs in the PM unit.\n");
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return 1;
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case 0x1234: // Dummy for non-existent functionality
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printf("This southbridge does not have GPIOBASE.\n");
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return 1;
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@ -29,6 +29,9 @@ static const struct {
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uint16_t vendor_id, device_id;
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char *name;
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} supported_chips_list[] = {
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX, "82443LX" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX, "82443BX" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_NO_AGP, "82443BX without AGP" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810, "i810" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810DC, "i810-DC100" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "i845" },
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@ -47,7 +50,8 @@ static const struct {
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4, "ICH4" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH2, "ICH2" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH0, "ICH0" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" }
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "82371AB/EB/MB" },
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};
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#ifndef __DARWIN__
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@ -112,7 +116,7 @@ void print_usage(const char *name)
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int main(int argc, char *argv[])
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{
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struct pci_access *pacc;
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struct pci_dev *sb, *nb;
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struct pci_dev *sb = NULL, *nb, *dev;
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int i, opt, option_index = 0;
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unsigned int id;
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@ -204,8 +208,20 @@ int main(int argc, char *argv[])
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pci_scan_bus(pacc);
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/* Find the required devices */
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for (dev = pacc->devices; dev; dev = dev->next) {
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pci_fill_info(dev, PCI_FILL_CLASS);
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/* The ISA/LPC bridge can be 0x1f, 0x07, or 0x04 so we probe. */
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if (dev->device_class == 0x0601) { /* ISA/LPC bridge */
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if (sb == NULL)
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sb = dev;
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else
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fprintf(stderr, "Multiple devices with class ID"
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" 0x0601, using %02x%02x:%02x.%02x\n",
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dev->domain, dev->bus, dev->dev,
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dev->func);
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}
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}
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sb = pci_get_dev(pacc, 0, 0, 0x1f, 0);
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if (!sb) {
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printf("No southbridge found.\n");
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exit(1);
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@ -32,27 +32,36 @@
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#define INTELTOOL_VERSION "1.0"
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/* Tested chipsets: */
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#define PCI_VENDOR_ID_INTEL 0x8086
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#define PCI_DEVICE_ID_INTEL_ICH 0x2410
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#define PCI_DEVICE_ID_INTEL_ICH0 0x2420
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#define PCI_DEVICE_ID_INTEL_ICH2 0x2440
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#define PCI_DEVICE_ID_INTEL_ICH4 0x24c0
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#define PCI_DEVICE_ID_INTEL_ICH4M 0x24cc
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#define PCI_DEVICE_ID_INTEL_ICH7DH 0x27b0
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#define PCI_DEVICE_ID_INTEL_ICH7 0x27b8
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#define PCI_DEVICE_ID_INTEL_ICH7M 0x27b9
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#define PCI_DEVICE_ID_INTEL_ICH7MDH 0x27bd
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#define PCI_DEVICE_ID_INTEL_ICH8M 0x2815
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#define PCI_DEVICE_ID_INTEL_ICH10R 0x3a16
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#define PCI_VENDOR_ID_INTEL 0x8086
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#define PCI_DEVICE_ID_INTEL_ICH 0x2410
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#define PCI_DEVICE_ID_INTEL_ICH0 0x2420
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#define PCI_DEVICE_ID_INTEL_ICH2 0x2440
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#define PCI_DEVICE_ID_INTEL_ICH4 0x24c0
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#define PCI_DEVICE_ID_INTEL_ICH4M 0x24cc
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#define PCI_DEVICE_ID_INTEL_ICH7DH 0x27b0
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#define PCI_DEVICE_ID_INTEL_ICH7 0x27b8
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#define PCI_DEVICE_ID_INTEL_ICH7M 0x27b9
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#define PCI_DEVICE_ID_INTEL_ICH7MDH 0x27bd
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#define PCI_DEVICE_ID_INTEL_ICH8M 0x2815
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#define PCI_DEVICE_ID_INTEL_ICH10R 0x3a16
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#define PCI_DEVICE_ID_INTEL_82810 0x7120
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#define PCI_DEVICE_ID_INTEL_82810DC 0x7122
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#define PCI_DEVICE_ID_INTEL_82845 0x1a30
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#define PCI_DEVICE_ID_INTEL_82945P 0x2770
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#define PCI_DEVICE_ID_INTEL_82945GM 0x27a0
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#define PCI_DEVICE_ID_INTEL_PM965 0x2a00
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#define PCI_DEVICE_ID_INTEL_82975X 0x277c
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#define PCI_DEVICE_ID_INTEL_X58 0x3405
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#define PCI_DEVICE_ID_INTEL_82810 0x7120
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#define PCI_DEVICE_ID_INTEL_82810DC 0x7122
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#define PCI_DEVICE_ID_INTEL_82845 0x1a30
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#define PCI_DEVICE_ID_INTEL_82945P 0x2770
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#define PCI_DEVICE_ID_INTEL_82945GM 0x27a0
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#define PCI_DEVICE_ID_INTEL_PM965 0x2a00
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#define PCI_DEVICE_ID_INTEL_82975X 0x277c
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#define PCI_DEVICE_ID_INTEL_X58 0x3405
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#define PCI_DEVICE_ID_INTEL_82443LX 0x7180
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/* 82443BX has a different device ID if AGP is disabled (hardware-wise). */
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#define PCI_DEVICE_ID_INTEL_82443BX 0x7190
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#define PCI_DEVICE_ID_INTEL_82443BX_NO_AGP 0x7192
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/* 82371AB/EB/MB use the same device ID value. */
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#define PCI_DEVICE_ID_INTEL_82371XX 0x7110
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#define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0])))
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@ -43,6 +43,8 @@ int print_mchbar(struct pci_dev *nb)
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mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
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mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
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break;
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case PCI_DEVICE_ID_INTEL_82443LX:
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case PCI_DEVICE_ID_INTEL_82443BX:
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case PCI_DEVICE_ID_INTEL_82810:
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case PCI_DEVICE_ID_INTEL_82810DC:
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printf("This northbrigde does not have MCHBAR.\n");
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@ -203,6 +203,50 @@ static const io_register_t ich0_pm_registers[] = {
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{ 0x7c, 4, "RESERVED" },
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};
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static const io_register_t i82371xx_pm_registers[] = {
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{ 0x00, 2, "PMSTS" },
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{ 0x02, 2, "PMEN" },
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{ 0x04, 2, "PMCNTRL" },
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{ 0x06, 2, "RESERVED" },
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{ 0x08, 1, "PMTMR" },
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{ 0x09, 1, "RESERVED" },
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{ 0x0A, 1, "RESERVED" },
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{ 0x0B, 1, "RESERVED" },
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{ 0x0C, 2, "GPSTS" },
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{ 0x0E, 2, "GPEN" },
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{ 0x10, 4, "PCNTRL" },
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#if DANGEROUS_REGISTERS
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/*
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* This register returns 0 on read, but reading it may cause
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* the system to enter C2 state, which might hang the system.
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*/
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{ 0x14, 1, "PLVL2" },
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{ 0x15, 1, "PLVL3" },
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{ 0x16, 2, "RESERVED" },
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#endif
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{ 0x18, 2, "GLBSTS" },
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{ 0x1A, 2, "RESERVED" },
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{ 0x1c, 4, "DEVSTS" },
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{ 0x20, 2, "GLBEN" },
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{ 0x22, 1, "RESERVED" },
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{ 0x23, 1, "RESERVED" },
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{ 0x24, 1, "RESERVED" },
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{ 0x25, 1, "RESERVED" },
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{ 0x26, 1, "RESERVED" },
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{ 0x27, 1, "RESERVED" },
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{ 0x28, 4, "GLBCTL" },
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{ 0x2C, 4, "DEVCTL" },
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/* The registers 0x30-0x33 and 0x34-0x37 allow byte-wise reads only. */
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{ 0x30, 1, "GPIREG 0" },
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{ 0x31, 1, "GPIREG 1" },
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{ 0x32, 1, "GPIREG 2" },
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{ 0x33, 1, "GPIREG 3" },
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{ 0x34, 1, "GPOREG 0" },
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{ 0x35, 1, "GPOREG 1" },
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{ 0x36, 1, "GPOREG 2" },
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{ 0x37, 1, "GPOREG 3" },
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};
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int print_pmbase(struct pci_dev *sb)
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{
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int i, size;
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@ -230,6 +274,11 @@ int print_pmbase(struct pci_dev *sb)
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pm_registers = ich0_pm_registers;
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size = ARRAY_SIZE(ich0_pm_registers);
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break;
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case PCI_DEVICE_ID_INTEL_82371XX:
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pmbase = pci_read_word(sb, 0x40) & 0xfffc;
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pm_registers = i82371xx_pm_registers;
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size = ARRAY_SIZE(i82371xx_pm_registers);
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break;
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case 0x1234: // Dummy for non-existent functionality
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printf("This southbridge does not have PMBASE.\n");
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return 1;
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