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Add initial inteltool support for Intel 440BX/440LX and 82371AB/EB/MB. 

Signed-off-by: Maciej Pijanka <maciej.pijanka@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4694 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Maciej Pijanka 2009-09-30 17:05:46 +00:00 committed by Uwe Hermann
parent 2583dd2095
commit 90d17407d8
5 changed files with 102 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
util/inteltool/gpio.c
View File

@ -131,6 +131,9 @@ int print_gpios(struct pci_dev *sb)
gpio_registers = ich0_gpio_registers; gpio_registers = ich0_gpio_registers;
size = ARRAY_SIZE(ich0_gpio_registers); size = ARRAY_SIZE(ich0_gpio_registers);
break; break;
case PCI_DEVICE_ID_INTEL_82371XX:
printf("This southbridge has GPIOs in the PM unit.\n");
return 1;
case 0x1234: // Dummy for non-existent functionality case 0x1234: // Dummy for non-existent functionality
printf("This southbridge does not have GPIOBASE.\n"); printf("This southbridge does not have GPIOBASE.\n");
return 1; return 1;

22
util/inteltool/inteltool.c
View File

@ -29,6 +29,9 @@ static const struct {
uint16_t vendor_id, device_id; uint16_t vendor_id, device_id;
char *name; char *name;
} supported_chips_list[] = { } supported_chips_list[] = {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX, "82443LX" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX, "82443BX" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_NO_AGP, "82443BX without AGP" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810, "i810" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810, "i810" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810DC, "i810-DC100" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810DC, "i810-DC100" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "i845" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "i845" },
@ -47,7 +50,8 @@ static const struct {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4, "ICH4" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4, "ICH4" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH2, "ICH2" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH2, "ICH2" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH0, "ICH0" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH0, "ICH0" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" } { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "82371AB/EB/MB" },
}; };
#ifndef __DARWIN__ #ifndef __DARWIN__
@ -112,7 +116,7 @@ void print_usage(const char *name)
int main(int argc, char *argv[]) int main(int argc, char *argv[])
{ {
struct pci_access *pacc; struct pci_access *pacc;
struct pci_dev *sb, *nb; struct pci_dev *sb = NULL, *nb, *dev;
int i, opt, option_index = 0; int i, opt, option_index = 0;
unsigned int id; unsigned int id;
@ -204,8 +208,20 @@ int main(int argc, char *argv[])
pci_scan_bus(pacc); pci_scan_bus(pacc);
/* Find the required devices */ /* Find the required devices */
for (dev = pacc->devices; dev; dev = dev->next) {
pci_fill_info(dev, PCI_FILL_CLASS);
/* The ISA/LPC bridge can be 0x1f, 0x07, or 0x04 so we probe. */
if (dev->device_class == 0x0601) { /* ISA/LPC bridge */
if (sb == NULL)
sb = dev;
else
fprintf(stderr, "Multiple devices with class ID"
" 0x0601, using %02x%02x:%02x.%02x\n",
dev->domain, dev->bus, dev->dev,
dev->func);
}
}
sb = pci_get_dev(pacc, 0, 0, 0x1f, 0);
if (!sb) { if (!sb) {
printf("No southbridge found.\n"); printf("No southbridge found.\n");
exit(1); exit(1);

49
util/inteltool/inteltool.h
View File

@ -32,27 +32,36 @@
#define INTELTOOL_VERSION "1.0" #define INTELTOOL_VERSION "1.0"
/* Tested chipsets: */ /* Tested chipsets: */
#define PCI_VENDOR_ID_INTEL 0x8086 #define PCI_VENDOR_ID_INTEL 0x8086
#define PCI_DEVICE_ID_INTEL_ICH 0x2410 #define PCI_DEVICE_ID_INTEL_ICH 0x2410
#define PCI_DEVICE_ID_INTEL_ICH0 0x2420 #define PCI_DEVICE_ID_INTEL_ICH0 0x2420
#define PCI_DEVICE_ID_INTEL_ICH2 0x2440 #define PCI_DEVICE_ID_INTEL_ICH2 0x2440
#define PCI_DEVICE_ID_INTEL_ICH4 0x24c0 #define PCI_DEVICE_ID_INTEL_ICH4 0x24c0
#define PCI_DEVICE_ID_INTEL_ICH4M 0x24cc #define PCI_DEVICE_ID_INTEL_ICH4M 0x24cc
#define PCI_DEVICE_ID_INTEL_ICH7DH 0x27b0 #define PCI_DEVICE_ID_INTEL_ICH7DH 0x27b0
#define PCI_DEVICE_ID_INTEL_ICH7 0x27b8 #define PCI_DEVICE_ID_INTEL_ICH7 0x27b8
#define PCI_DEVICE_ID_INTEL_ICH7M 0x27b9 #define PCI_DEVICE_ID_INTEL_ICH7M 0x27b9
#define PCI_DEVICE_ID_INTEL_ICH7MDH 0x27bd #define PCI_DEVICE_ID_INTEL_ICH7MDH 0x27bd
#define PCI_DEVICE_ID_INTEL_ICH8M 0x2815 #define PCI_DEVICE_ID_INTEL_ICH8M 0x2815
#define PCI_DEVICE_ID_INTEL_ICH10R 0x3a16 #define PCI_DEVICE_ID_INTEL_ICH10R 0x3a16
#define PCI_DEVICE_ID_INTEL_82810 0x7120 #define PCI_DEVICE_ID_INTEL_82810 0x7120
#define PCI_DEVICE_ID_INTEL_82810DC 0x7122 #define PCI_DEVICE_ID_INTEL_82810DC 0x7122
#define PCI_DEVICE_ID_INTEL_82845 0x1a30 #define PCI_DEVICE_ID_INTEL_82845 0x1a30
#define PCI_DEVICE_ID_INTEL_82945P 0x2770 #define PCI_DEVICE_ID_INTEL_82945P 0x2770
#define PCI_DEVICE_ID_INTEL_82945GM 0x27a0 #define PCI_DEVICE_ID_INTEL_82945GM 0x27a0
#define PCI_DEVICE_ID_INTEL_PM965 0x2a00 #define PCI_DEVICE_ID_INTEL_PM965 0x2a00
#define PCI_DEVICE_ID_INTEL_82975X 0x277c #define PCI_DEVICE_ID_INTEL_82975X 0x277c
#define PCI_DEVICE_ID_INTEL_X58 0x3405 #define PCI_DEVICE_ID_INTEL_X58 0x3405
#define PCI_DEVICE_ID_INTEL_82443LX 0x7180
/* 82443BX has a different device ID if AGP is disabled (hardware-wise). */
#define PCI_DEVICE_ID_INTEL_82443BX 0x7190
#define PCI_DEVICE_ID_INTEL_82443BX_NO_AGP 0x7192
/* 82371AB/EB/MB use the same device ID value. */
#define PCI_DEVICE_ID_INTEL_82371XX 0x7110
#define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0]))) #define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0])))

2
util/inteltool/memory.c
View File

@ -43,6 +43,8 @@ int print_mchbar(struct pci_dev *nb)
mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
break; break;
case PCI_DEVICE_ID_INTEL_82443LX:
case PCI_DEVICE_ID_INTEL_82443BX:
case PCI_DEVICE_ID_INTEL_82810: case PCI_DEVICE_ID_INTEL_82810:
case PCI_DEVICE_ID_INTEL_82810DC: case PCI_DEVICE_ID_INTEL_82810DC:
printf("This northbrigde does not have MCHBAR.\n"); printf("This northbrigde does not have MCHBAR.\n");

49
util/inteltool/powermgt.c
View File

@ -203,6 +203,50 @@ static const io_register_t ich0_pm_registers[] = {
{ 0x7c, 4, "RESERVED" }, { 0x7c, 4, "RESERVED" },
}; };
static const io_register_t i82371xx_pm_registers[] = {
{ 0x00, 2, "PMSTS" },
{ 0x02, 2, "PMEN" },
{ 0x04, 2, "PMCNTRL" },
{ 0x06, 2, "RESERVED" },
{ 0x08, 1, "PMTMR" },
{ 0x09, 1, "RESERVED" },
{ 0x0A, 1, "RESERVED" },
{ 0x0B, 1, "RESERVED" },
{ 0x0C, 2, "GPSTS" },
{ 0x0E, 2, "GPEN" },
{ 0x10, 4, "PCNTRL" },
#if DANGEROUS_REGISTERS
/*
* This register returns 0 on read, but reading it may cause
* the system to enter C2 state, which might hang the system.
*/
{ 0x14, 1, "PLVL2" },
{ 0x15, 1, "PLVL3" },
{ 0x16, 2, "RESERVED" },
#endif
{ 0x18, 2, "GLBSTS" },
{ 0x1A, 2, "RESERVED" },
{ 0x1c, 4, "DEVSTS" },
{ 0x20, 2, "GLBEN" },
{ 0x22, 1, "RESERVED" },
{ 0x23, 1, "RESERVED" },
{ 0x24, 1, "RESERVED" },
{ 0x25, 1, "RESERVED" },
{ 0x26, 1, "RESERVED" },
{ 0x27, 1, "RESERVED" },
{ 0x28, 4, "GLBCTL" },
{ 0x2C, 4, "DEVCTL" },
/* The registers 0x30-0x33 and 0x34-0x37 allow byte-wise reads only. */
{ 0x30, 1, "GPIREG 0" },
{ 0x31, 1, "GPIREG 1" },
{ 0x32, 1, "GPIREG 2" },
{ 0x33, 1, "GPIREG 3" },
{ 0x34, 1, "GPOREG 0" },
{ 0x35, 1, "GPOREG 1" },
{ 0x36, 1, "GPOREG 2" },
{ 0x37, 1, "GPOREG 3" },
};
int print_pmbase(struct pci_dev *sb) int print_pmbase(struct pci_dev *sb)
{ {
int i, size; int i, size;
@ -230,6 +274,11 @@ int print_pmbase(struct pci_dev *sb)
pm_registers = ich0_pm_registers; pm_registers = ich0_pm_registers;
size = ARRAY_SIZE(ich0_pm_registers); size = ARRAY_SIZE(ich0_pm_registers);
break; break;
case PCI_DEVICE_ID_INTEL_82371XX:
pmbase = pci_read_word(sb, 0x40) & 0xfffc;
pm_registers = i82371xx_pm_registers;
size = ARRAY_SIZE(i82371xx_pm_registers);
break;
case 0x1234: // Dummy for non-existent functionality case 0x1234: // Dummy for non-existent functionality
printf("This southbridge does not have PMBASE.\n"); printf("This southbridge does not have PMBASE.\n");
return 1; return 1;