Add support for enabling PCIe Common Clock and ASPM
These are guarded by individual Kconfig entries. The deprecated CONFIG_PCIE_TUNING defines have been removed in favor of using specific config options. This is the generic half, there is board-specific pieces still to come that tune before and after ASPM is enabled. Change-Id: I3fe46282eada67629e9eeeed07e487dff54f2729 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/735 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
This commit is contained in:
Duncan Laurie
Stefan Reinauer
parent
22c0468d39
commit
90dcdd43ee
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@ -163,3 +163,17 @@ config AGP_PLUGIN_SUPPORT
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config CARDBUS_PLUGIN_SUPPORT
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bool
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default y
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config PCIEXP_COMMON_CLOCK
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prompt "Enable PCIe Common Clock"
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bool
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default n
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help
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Detect and enable Common Clock on PCIe links.
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config PCIEXP_ASPM
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prompt "Enable PCIe ASPM"
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bool
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default n
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help
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Detect and enable ASPM on PCIe links.
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@ -19,31 +19,197 @@
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*/
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#include <console/console.h>
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#include <delay.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pciexp.h>
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#if CONFIG_PCIEXP_COMMON_CLOCK
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/*
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* Re-train a PCIe link
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*/
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#define PCIE_TRAIN_RETRY 10000
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static int pciexp_retrain_link(device_t dev, unsigned cap)
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{
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unsigned try = PCIE_TRAIN_RETRY;
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u16 lnk;
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/* Start link retraining */
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lnk = pci_read_config16(dev, cap + PCI_EXP_LNKCTL);
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lnk |= PCI_EXP_LNKCTL_RL;
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pci_write_config16(dev, cap + PCI_EXP_LNKCTL, lnk);
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/* Wait for training to complete */
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while (try--) {
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lnk = pci_read_config16(dev, cap + PCI_EXP_LNKSTA);
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if (!(lnk & PCI_EXP_LNKSTA_LT))
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return 0;
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udelay(100);
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}
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printk(BIOS_ERR, "%s: Link Retrain timeout\n", dev_path(dev));
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return -1;
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}
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/*
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* Check the Slot Clock Configuration for root port and endpoint
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* and enable Common Clock Configuration if possible. If CCC is
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* enabled the link must be retrained.
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*/
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static void pciexp_enable_common_clock(device_t root, unsigned root_cap,
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device_t endp, unsigned endp_cap)
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{
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u16 root_scc, endp_scc, lnkctl;
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/* Get Slot Clock Configuration for root port */
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root_scc = pci_read_config16(root, root_cap + PCI_EXP_LNKSTA);
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root_scc &= PCI_EXP_LNKSTA_SLC;
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/* Get Slot Clock Configuration for endpoint */
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endp_scc = pci_read_config16(endp, endp_cap + PCI_EXP_LNKSTA);
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endp_scc &= PCI_EXP_LNKSTA_SLC;
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/* Enable Common Clock Configuration and retrain */
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if (root_scc && endp_scc) {
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printk(BIOS_INFO, "Enabling Common Clock Configuration\n");
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/* Set in endpoint */
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lnkctl = pci_read_config16(endp, endp_cap + PCI_EXP_LNKCTL);
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lnkctl |= PCI_EXP_LNKCTL_CCC;
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pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl);
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/* Set in root port */
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lnkctl = pci_read_config16(root, root_cap + PCI_EXP_LNKCTL);
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lnkctl |= PCI_EXP_LNKCTL_CCC;
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pci_write_config16(root, root_cap + PCI_EXP_LNKCTL, lnkctl);
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/* Retrain link if CCC was enabled */
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pciexp_retrain_link(root, root_cap);
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}
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}
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#endif /* CONFIG_PCIEXP_COMMON_CLOCK */
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#if CONFIG_PCIEXP_ASPM
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/*
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* Determine the ASPM L0s or L1 exit latency for a link
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* by checking both root port and endpoint and returning
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* the highest latency value.
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*/
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static int pciexp_aspm_latency(device_t root, unsigned root_cap,
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device_t endp, unsigned endp_cap,
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enum aspm_type type)
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{
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int root_lat = 0, endp_lat = 0;
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u32 root_lnkcap, endp_lnkcap;
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root_lnkcap = pci_read_config32(root, root_cap + PCI_EXP_LNKCAP);
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endp_lnkcap = pci_read_config32(endp, endp_cap + PCI_EXP_LNKCAP);
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/* Make sure the link supports this ASPM type by checking
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* capability bits 11:10 with aspm_type offset by 1 */
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if (!(root_lnkcap & (1 << (type + 9))) ||
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!(endp_lnkcap & (1 << (type + 9))))
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return -1;
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/* Find the one with higher latency */
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switch (type) {
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case PCIE_ASPM_L0S:
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root_lat = (root_lnkcap & PCI_EXP_LNKCAP_L0SEL) >> 12;
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endp_lat = (endp_lnkcap & PCI_EXP_LNKCAP_L0SEL) >> 12;
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break;
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case PCIE_ASPM_L1:
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root_lat = (root_lnkcap & PCI_EXP_LNKCAP_L1EL) >> 15;
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endp_lat = (endp_lnkcap & PCI_EXP_LNKCAP_L1EL) >> 15;
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break;
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default:
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return -1;
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}
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return (endp_lat > root_lat) ? endp_lat : root_lat;
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}
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/*
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* Enable ASPM on PCIe root port and endpoint.
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*
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* Returns APMC value:
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* -1 = Error
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* 0 = no ASPM
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* 1 = L0s Enabled
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* 2 = L1 Enabled
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* 3 = L0s and L1 Enabled
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*/
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static enum aspm_type pciexp_enable_aspm(device_t root, unsigned root_cap,
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device_t endp, unsigned endp_cap)
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{
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const char *aspm_type_str[] = { "None", "L0s", "L1", "L0s and L1" };
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enum aspm_type apmc = PCIE_ASPM_NONE;
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int exit_latency, ok_latency;
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u16 lnkctl;
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u32 devcap;
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/* Get endpoint device capabilities for acceptable limits */
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devcap = pci_read_config32(endp, endp_cap + PCI_EXP_DEVCAP);
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/* Enable L0s if it is within endpoint acceptable limit */
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ok_latency = (devcap & PCI_EXP_DEVCAP_L0S) >> 6;
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exit_latency = pciexp_aspm_latency(root, root_cap, endp, endp_cap,
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PCIE_ASPM_L0S);
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if (exit_latency >= 0 && exit_latency <= ok_latency)
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apmc |= PCIE_ASPM_L0S;
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/* Enable L1 if it is within endpoint acceptable limit */
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ok_latency = (devcap & PCI_EXP_DEVCAP_L1) >> 9;
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exit_latency = pciexp_aspm_latency(root, root_cap, endp, endp_cap,
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PCIE_ASPM_L1);
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if (exit_latency >= 0 && exit_latency <= ok_latency)
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apmc |= PCIE_ASPM_L1;
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if (apmc != PCIE_ASPM_NONE) {
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/* Set APMC in root port first */
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lnkctl = pci_read_config16(root, root_cap + PCI_EXP_LNKCTL);
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lnkctl |= apmc;
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pci_write_config16(root, root_cap + PCI_EXP_LNKCTL, lnkctl);
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/* Set APMC in endpoint device next */
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lnkctl = pci_read_config16(endp, endp_cap + PCI_EXP_LNKCTL);
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lnkctl |= apmc;
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pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl);
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}
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printk(BIOS_INFO, "ASPM: Enabled %s\n", aspm_type_str[apmc]);
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return apmc;
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}
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#endif /* CONFIG_PCIEXP_ASPM */
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static void pciexp_tune_dev(device_t dev)
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{
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unsigned int cap;
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#if CONFIG_PCIE_TUNING
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u32 reg32;
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#endif
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device_t root = dev->bus->dev;
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unsigned int root_cap, cap;
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cap = pci_find_capability(dev, PCI_CAP_ID_PCIE);
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if (!cap)
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return;
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#if CONFIG_PCIE_TUNING
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printk(BIOS_DEBUG, "PCIe: tuning %s\n", dev_path(dev));
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root_cap = pci_find_capability(root, PCI_CAP_ID_PCIE);
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if (!root_cap)
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return;
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// TODO make this depending on ASPM.
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#if CONFIG_PCIEXP_COMMON_CLOCK
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/* Check for and enable Common Clock */
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pciexp_enable_common_clock(root, root_cap, dev, cap);
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#endif
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/* Enable ASPM role based error reporting. */
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reg32 = pci_read_config32(dev, cap + PCI_EXP_DEVCAP);
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reg32 |= PCI_EXP_DEVCAP_RBER;
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pci_write_config32(dev, cap + PCI_EXP_DEVCAP, reg32);
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#if CONFIG_PCIEXP_ASPM
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/* Check for and enable ASPM */
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enum aspm_type apmc = pciexp_enable_aspm(root, root_cap, dev, cap);
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if (apmc != PCIE_ASPM_NONE) {
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/* Enable ASPM role based error reporting. */
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u32 reg32 = pci_read_config32(dev, cap + PCI_EXP_DEVCAP);
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reg32 |= PCI_EXP_DEVCAP_RBER;
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pci_write_config32(dev, cap + PCI_EXP_DEVCAP, reg32);
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}
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#endif
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}
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@ -371,8 +371,15 @@
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#define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
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#define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
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#define PCI_EXP_LNKCAP 12 /* Link Capabilities */
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#define PCI_EXP_LNKCAP_ASPMS 0xc00 /* ASPM Support */
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#define PCI_EXP_LNKCAP_L0SEL 0x7000 /* L0s Exit Latency */
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#define PCI_EXP_LNKCAP_L1EL 0x38000 /* L1 Exit Latency */
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#define PCI_EXP_LNKCTL 16 /* Link Control */
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#define PCI_EXP_LNKCTL_RL 0x20 /* Retrain Link */
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#define PCI_EXP_LNKCTL_CCC 0x40 /* Common Clock COnfiguration */
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#define PCI_EXP_LNKSTA 18 /* Link Status */
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#define PCI_EXP_LNKSTA_LT 0x800 /* Link Training */
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#define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */
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#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
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#define PCI_EXP_SLTCTL 24 /* Slot Control */
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#define PCI_EXP_SLTSTA 26 /* Slot Status */
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@ -2,6 +2,13 @@
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#define DEVICE_PCIEXP_H
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/* (c) 2005 Linux Networx GPL see COPYING for details */
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enum aspm_type {
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PCIE_ASPM_NONE = 0,
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PCIE_ASPM_L0S = 1,
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PCIE_ASPM_L1 = 2,
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PCIE_ASPM_BOTH = 3,
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};
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unsigned int pciexp_scan_bus(struct bus *bus, unsigned int min_devfn,
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unsigned int max_devfn, unsigned int max);
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unsigned int pciexp_scan_bridge(device_t dev, unsigned int max);
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