diff --git a/src/mainboard/intel/amenia/Kconfig b/src/mainboard/intel/amenia/Kconfig
index 6fc5e35c9f..b3ef17bef4 100644
--- a/src/mainboard/intel/amenia/Kconfig
+++ b/src/mainboard/intel/amenia/Kconfig
@@ -44,4 +44,10 @@ config MAX_CPUS
 	int
 	default 8
 
+config INCLUDE_NHLT_BLOBS
+	bool "Include blobs for audio."
+	select NHLT_DMIC_2CH_16B
+	select NHLT_DA7219
+	select NHLT_MAX98357
+
 endif # BOARD_INTEL_AMENIA
diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl
index 4a64f87382..46404ed7ff 100644
--- a/src/mainboard/intel/amenia/dsdt.asl
+++ b/src/mainboard/intel/amenia/dsdt.asl
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2016 Intel Corp.
  * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
  *
  * This program is free software; you can redistribute it and/or modify
@@ -33,15 +33,16 @@ DefinitionBlock(
 	Scope (\_SB) {
 		Device (PCI0)
 		{
-                #include <soc/intel/apollolake/acpi/northbridge.asl>
-                #include <soc/intel/apollolake/acpi/southbridge.asl>
+			#include <soc/intel/apollolake/acpi/northbridge.asl>
+			#include <soc/intel/apollolake/acpi/southbridge.asl>
+			#include <soc/intel/apollolake/acpi/pch_hda.asl>
 		}
 	}
 	/* Mainboard Specific devices */
 	#include "acpi/mainboard.asl"
 
-        /* Chipset specific sleep states */
-        #include <soc/intel/apollolake/acpi/sleepstates.asl>
+	/* Chipset specific sleep states */
+	#include <soc/intel/apollolake/acpi/sleepstates.asl>
 
 	#include "acpi/superio.asl"
 }
diff --git a/src/mainboard/intel/amenia/mainboard.c b/src/mainboard/intel/amenia/mainboard.c
index 8d10b28700..6ec5b98328 100644
--- a/src/mainboard/intel/amenia/mainboard.c
+++ b/src/mainboard/intel/amenia/mainboard.c
@@ -15,9 +15,10 @@
  * GNU General Public License for more details.
  */
 
+#include <arch/acpi.h>
+#include <console/console.h>
 #include <device/device.h>
-#include <soc/gpio.h>
-#include <soc/pci_devs.h>
+#include <soc/nhlt.h>
 #include "ec.h"
 #include "gpio.h"
 
@@ -27,6 +28,49 @@ static void mainboard_init(void *chip_info)
 	mainboard_ec_init();
 }
 
+static unsigned long mainboard_write_acpi_tables(
+        device_t device, unsigned long current, acpi_rsdp_t *rsdp)
+{
+	uintptr_t start_addr;
+	uintptr_t end_addr;
+	struct nhlt *nhlt;
+
+	start_addr = current;
+
+	nhlt = nhlt_init();
+
+	if (nhlt == NULL)
+		return start_addr;
+
+	/* 2 Channel DMIC array. */
+	if (!nhlt_soc_add_dmic_array(nhlt, 2))
+		printk(BIOS_ERR, "Added 2CH DMIC array.\n");
+
+	/* Dialog for Headset codec.
+	 * Headset codec is bi-directional but uses the same configuration
+	 * settings for render and capture endpoints.
+	 */
+	if (!nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP1))
+		printk(BIOS_ERR, "Added Dialog_7219 codec.\n");
+
+	/* MAXIM Smart Amps for left and right speakers. */
+	if (!nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP5))
+		printk(BIOS_ERR, "Added Maxim_98357 codec.\n");
+
+	end_addr = nhlt_soc_serialize(nhlt, start_addr);
+
+	if (end_addr != start_addr)
+		acpi_add_table(rsdp, (void *)start_addr);
+
+	return end_addr;
+}
+
+static void mainboard_enable(device_t dev)
+{
+	dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
+}
+
 struct chip_operations mainboard_ops = {
 	.init = mainboard_init,
+	.enable_dev = mainboard_enable,
 };