diff --git a/src/soc/qualcomm/sdm845/Makefile.inc b/src/soc/qualcomm/sdm845/Makefile.inc
index 1fddb56345..e603177317 100644
--- a/src/soc/qualcomm/sdm845/Makefile.inc
+++ b/src/soc/qualcomm/sdm845/Makefile.inc
@@ -7,6 +7,7 @@ bootblock-y += spi.c
 bootblock-y += mmu.c
 bootblock-y += timer.c
 bootblock-y += gpio.c
+bootblock-$(CONFIG_DRIVERS_UART) += uart_bitbang.c
 
 ################################################################################
 verstage-y += spi.c
diff --git a/src/soc/qualcomm/sdm845/uart_bitbang.c b/src/soc/qualcomm/sdm845/uart_bitbang.c
new file mode 100644
index 0000000000..f39e0ef1ae
--- /dev/null
+++ b/src/soc/qualcomm/sdm845/uart_bitbang.c
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/uart.h>
+#include <gpio.h>
+#include <types.h>
+
+#define UART_TX_PIN GPIO(4)
+
+static void set_tx(int line_state)
+{
+	gpio_set(UART_TX_PIN, line_state);
+}
+
+void uart_init(int idx)
+{
+	gpio_output(UART_TX_PIN, 1);
+}
+
+void uart_tx_byte(int idx, unsigned char data)
+{
+	uart_bitbang_tx_byte(data, set_tx);
+}
+
+void uart_tx_flush(int idx)
+{
+	/* unnecessary, PIO Tx means transaction is over when tx_byte returns */
+}
+
+unsigned char uart_rx_byte(int idx)
+{
+	return 0;	/* not implemented */
+}