Documentation: More markdown fixes after switching to sphinx
Fix markdown code to work with sphinx. Change-Id: I52014494dc2d09731fe14ab527073352ada860d1 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/26544 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Patrick Rudolph
Philipp Deppenwiese
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@ -10,15 +10,15 @@ Today coreboot is capable enough to handle multi-processor initialization on IA
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The multi-processor initialization code has to take care of lots of duties:
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1 Bringing all cores out of reset
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2 Load latest microcode on all cores
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3 Sync latest MTRR snapshot between BSP and APs
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4 Perform sets of CPU feature programming
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* CPU Power & Thermal Management
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* Overclocking
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* Intel Trusted Execution Technology
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* Intel Software Guard Extensions
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* Intel Processor Trace etc.
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1. Bringing all cores out of reset
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2. Load latest microcode on all cores
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3. Sync latest MTRR snapshot between BSP and APs
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4. Perform sets of CPU feature programming
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* CPU Power & Thermal Management
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* Overclocking
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* Intel Trusted Execution Technology
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* Intel Software Guard Extensions
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* Intel Processor Trace etc.
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This above CPU feature programming lists are expected to grow with current and future
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CPU complexity and there might be some cases where certain feature programming mightbe
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@ -39,30 +39,39 @@ programming using coreboot published APIs.
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Due to the fact that FSP is using EFI infrastructure and need to relying on install/locate
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PPI to perform certain API call, hence coreboot has to created MP services APIs known as
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EFI_MP_SERVICES_PPI as per PI specification volume 1, section 8.3.9.
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More details here: http://www.uefi.org/sites/default/files/resources/PI_Spec_1_6.pdf
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More details here: [PI_Spec_1_6]
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### coreboot to publish EFI_MP_SERVICES_PPI APIs
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| API | Description |
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|------------------------------|------------------------------------------------------------------|
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| PeiGetNumberOfProcessors | Get the number of CPU's. |
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| PeiGetProcessorInfo | Get information on a specific CPU. |
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| PeiStartupAllAPs | Activate all of the application processors. |
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| PeiStartupThisAP | Activate a specific application processor. |
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| PeiSwitchBSP | Switch the boot strap processor. |
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| PeiEnableDisableAP | Enable or disable an application processor. |
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| PeiWhoAmI | Identify the currently executing processor. |
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|------------------------------|------------------------------------------------------------------|
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```eval_rst
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+------------------------------+------------------------------------------------------------------+
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| API | Description |
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+==============================+==================================================================+
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| PeiGetNumberOfProcessors | Get the number of CPU's. |
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+------------------------------+------------------------------------------------------------------+
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| PeiGetProcessorInfo | Get information on a specific CPU. |
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+------------------------------+------------------------------------------------------------------+
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| PeiStartupAllAPs | Activate all of the application processors. |
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+------------------------------+------------------------------------------------------------------+
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| PeiStartupThisAP | Activate a specific application processor. |
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+------------------------------+------------------------------------------------------------------+
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| PeiSwitchBSP | Switch the boot strap processor. |
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+------------------------------+------------------------------------------------------------------+
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| PeiEnableDisableAP | Enable or disable an application processor. |
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+------------------------------+------------------------------------------------------------------+
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| PeiWhoAmI | Identify the currently executing processor. |
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+------------------------------+------------------------------------------------------------------+
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```
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## Code Flow
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Here is proposed design flow with coreboot has implemented EFI_MP_SERVICES_PPI API and FSP will make
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use of the same to perform some CPU feature programming.
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** coreboot-FSP MP init flow **
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![alt text][coreboot_publish_mp_service_api]
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**coreboot-FSP MP init flow**
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![coreboot-fsp mp init flow][coreboot_publish_mp_service_api]
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[coreboot_publish_mp_service_api]: coreboot_publish_mp_service_api.png "coreboot-fsp mp init flow"
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[coreboot_publish_mp_service_api]: coreboot_publish_mp_service_api.png
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## Benefits
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1. coreboot was using SkipMpInit=1 which will skip entire FSP CPU feature programming.
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@ -72,3 +81,5 @@ Silicon recommended CPU programming.
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coreboot interfaces to execute those programming.
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3. coreboot will have more control over running those feature programming as API optimization
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handled by coreboot.
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[PI_Spec_1_6]: http://www.uefi.org/sites/default/files/resources/PI_Spec_1_6.pdf
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@ -69,7 +69,7 @@ It is possible to override the soft fuses limit by using a board-specific
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> **Note:** Ignoring max mem freq. fuses is supported since coreboot 4.7.
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## <a name="hard_fuses"></a> Hard fuses
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## Hard fuses
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"Hard" fuses are programmed by Intel and limit the maximum frequency that can
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be used on a given CPU/board/chipset. At time of writing there's no register
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to read this limit, before trying to set a given DRAM frequency. The memory PLL
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@ -77,8 +77,8 @@ won't lock, indicating that the chosen memory multiplier isn't available. In
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this case coreboot tries the next smaller memory multiplier until the PLL will
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lock.
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## <a name="devicetree"></a> Devicetree
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The devicetree register ```max_mem_clock_mhz``` overrides the "soft" fuses set
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## Devicetree
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The devicetree register `max_mem_clock_mhz` overrides the "soft" fuses set
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by the board manufacturer.
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By using this register it's possible to force a minimum operating frequency.
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@ -78,20 +78,20 @@ The highest IO delay was set on the right-hand side, while the last block
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on the left-hand side has zero IO delay.
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#### roundtrip 55 DCKs
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![alt text][timA_lane0-3_rt55]
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![timA for lane0 - lane3, roundtrip 55][timA_lane0-3_rt55]
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[timA_lane0-3_rt55]: timA_lane0-3_rt55.png "timA for lane0 - lane3, roundtrip 55"
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[timA_lane0-3_rt55]: timA_lane0-3_rt55.png
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#### roundtrip 54 DCKs
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![alt text][timA_lane0-3_rt54]
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![timA for lane0 - lane3, roundtrip 54][timA_lane0-3_rt54]
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[timA_lane0-3_rt54]: timA_lane0-3_rt54.png "timA for lane0 - lane3, roundtrip 54"
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[timA_lane0-3_rt54]: timA_lane0-3_rt54.png
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#### roundtrip 53 DCKs
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![alt text][timA_lane0-3_rt53]
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![timA for lane0 - lane3, roundtrip 53][timA_lane0-3_rt53]
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[timA_lane0-3_rt53]: timA_lane0-3_rt53.png "timA for lane0 - lane3, roundtrip 53"
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[timA_lane0-3_rt53]: timA_lane0-3_rt53.png
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As you can see the signal has some jitter as every sample was taken in a
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different loop iteration. The result register only contains a single bit per
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@ -128,13 +128,13 @@ If it's "high" we have found the preamble.
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The roundtrip time and IO delay will be adjusted until all lanes are aligned.
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The resulting IO delay is visible in the picture below.
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** roundtrip time: 49 DCKs, IO delay (at blue point): 6 DCKs **
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![alt text][timA_lane0-3_discover_420x]
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**roundtrip time: 49 DCKs, IO delay (at blue point): 6 DCKs**
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![timA for lane0 - lane3, finding minimum roundtrip time][timA_lane0-3_discover_420x]
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[timA_lane0-3_discover_420x]: timA_lane0-3_discover_420x.png "timA for lane0 - lane3, finding minimum roundtrip time"
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[timA_lane0-3_discover_420x]: timA_lane0-3_discover_420x.png
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** Note: The sampled data has been shifted by timA. The preamble is now
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in phase. **
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**Note: The sampled data has been shifted by timA. The preamble is now
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in phase.**
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## Fine adjustment
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@ -146,8 +146,8 @@ times. The fine adjustment finds the middle of each rising edge (it's actual
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the falling edge of the preamble) to get the final IO phase. You can see the
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result in the picture below.
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![alt text][timA_lane0-3_adjust_fine]
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![timA for lane0 - lane3, fine adjustment][timA_lane0-3_adjust_fine]
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[timA_lane0-3_adjust_fine]: timA_lane0-3_adjust_fine.png "timA for lane0 - lane3, fine adjustment"
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[timA_lane0-3_adjust_fine]: timA_lane0-3_adjust_fine.png
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Lanes 0 - 2 will be adjusted by a phase of -10, while lane 3 is already correct.
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