soc/intel/apollolake: Use fixed resource for SRAM and IPC1

Intel telemetry support will require PMC IPC1 and SRAM devices to be
operated in ACPI mode. Then using fixed resources on BAR0, BAR1
and BAR2 (PMC only) for those two devices will help
the resource assignment in DSDT stage.

BUG=chrome-os-partner:57364
BRANCH=None
TEST=Boot up into Chrome OS successfully and check with dmesg to see
the driver has been loaded successfully without errors.

Change-Id: I8f0983a90728b9148a124ae3443ec29cd7b344ce
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/16648
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/apollolake/Makefile.inc

@@ -71,6 +71,7 @@ ramstage-y += pmutil.c
 ramstage-y += pmc.c
 ramstage-y += reset.c
 ramstage-y += smi.c
+ramstage-y += sram.c
 ramstage-y += spi.c
 ramstage-y += xhci.c
 

src/soc/intel/apollolake/include/soc/iomap.h

@@ -32,6 +32,12 @@
 /* Accesses to these BARs are hardcoded in FSP */
 #define PMC_BAR0			0xfe042000
 #define PMC_BAR1			0xfe044000
+#define PMC_BAR0_SIZE			(8 * KiB)
+
+#define PMC_SRAM_BASE_0			0xfe900000
+#define PMC_SRAM_SIZE_0			(8 * KiB)
+#define PMC_SRAM_BASE_1			0xfe902000
+#define PMC_SRAM_SIZE_1			(4 * KiB)
 
 /* Temporary BAR for SPI until PCI enumeration assigns a BAR in ramstage. */
 #define PRERAM_SPI_BASE_ADDRESS		0xfe010000

src/soc/intel/apollolake/include/soc/pci_ids.h

@@ -24,6 +24,7 @@
 #define PCI_DEVICE_ID_APOLLOLAKE_P2SB		0x5a92		/* 00:0d.0 */
 #define PCI_DEVICE_ID_APOLLOLAKE_PMC		0x5a94		/* 00:0d.1 */
 #define PCI_DEVICE_ID_APOLLOLAKE_HWSEQ_SPI	0x5a96		/* 00:0d.2 */
+#define PCI_DEVICE_ID_APOLLOLAKE_SRAM		0x5aec		/* 00:0d.3 */
 #define PCI_DEVICE_ID_APOLLOLAKE_AUDIO		0x5a98		/* 00:0e.0 */
 #define PCI_DEVICE_ID_APOLLOLAKE_SATA		0x5ae0		/* 00:12.0 */
 #define PCI_DEVICE_ID_APOLLOLAKE_XHCI		0x5aa8		/* 00:15.0 */

src/soc/intel/apollolake/pmc.c

@@ -39,6 +39,11 @@ static void read_resources(device_t dev)
 	struct resource *res;
 	pci_dev_read_resources(dev);
 
+	res = new_resource(dev, PCI_BASE_ADDRESS_0);
+	res->base = PMC_BAR0;
+	res->size = PMC_BAR0_SIZE;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
 	res = new_resource(dev, PCI_BASE_ADDRESS_4);
 	res->base = ACPI_PMIO_BASE;
 	res->size = ACPI_PMIO_SIZE;
@@ -58,6 +63,12 @@ static void set_resources(device_t dev)
 
 	pci_dev_set_resources(dev);
 
+	res = find_resource(dev, PCI_BASE_ADDRESS_0);
+	pci_write_config32(dev, res->index, res->base);
+	dev->command |= PCI_COMMAND_MEMORY;
+	res->flags |= IORESOURCE_STORED;
+	report_resource_stored(dev, res, " PMC BAR");
+
 	res = find_resource(dev, PCI_BASE_ADDRESS_4);
 	pci_write_config32(dev, res->index, res->base);
 	dev->command |= PCI_COMMAND_IO;

src/soc/intel/apollolake/pmutil.c

@@ -34,8 +34,7 @@
 
 static uintptr_t read_pmc_mmio_bar(void)
 {
-	uint32_t bar = pci_read_config32(PMC_DEV, PCI_BASE_ADDRESS_0);
-	return bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
+	return PMC_BAR0;
 }
 
 uintptr_t get_pmc_mmio_bar(void)

src/soc/intel/apollolake/sram.c

@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <soc/pci_ids.h>
+#include <soc/pci_devs.h>
+#include <soc/iomap.h>
+
+static void read_resources(device_t dev)
+{
+	struct resource *res;
+	pci_dev_read_resources(dev);
+
+	res = new_resource(dev, PCI_BASE_ADDRESS_0);
+	res->base = PMC_SRAM_BASE_0;
+	res->size = PMC_SRAM_SIZE_0;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, PCI_BASE_ADDRESS_2);
+	res->base = PMC_SRAM_BASE_1;
+	res->size = PMC_SRAM_SIZE_1;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
+static void set_resources(device_t dev)
+{
+	struct resource *res;
+	pci_dev_set_resources(dev);
+
+	res = find_resource(dev, PCI_BASE_ADDRESS_0);
+	pci_write_config32(dev, res->index, res->base);
+	dev->command |= PCI_COMMAND_MEMORY;
+	res->flags |= IORESOURCE_STORED;
+	report_resource_stored(dev, res, " SRAM BAR 0");
+
+	res = find_resource(dev, PCI_BASE_ADDRESS_2);
+	pci_write_config32(dev, res->index, res->base);
+	dev->command |= PCI_COMMAND_MEMORY;
+	res->flags |= IORESOURCE_STORED;
+	report_resource_stored(dev, res, " SRAM BAR 1");
+}
+
+static const struct device_operations device_ops = {
+	.read_resources		= read_resources,
+	.set_resources		= set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+};
+
+static const struct pci_driver pmc __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_APOLLOLAKE_SRAM,
+};