Add support for A-Open DXPL Plus-U motherboard
This is an old (pre-2005) entry-level server mainboard. The code is adapted from mainboard/intel/xe7501devkit. Featured chips: - Dual socket604 - E7505 northbridge - 82801DB southbridge (with EHCI debug port) - 82870p2 PCI-X bridge - LPC47M102S-MC super-io - 512kB FWH flash (flashrom does the job well) What works: - Dual-Xeon P4/HT boot with microcode update - RAM: registered ECC DDR266 in dual-channel - PCI-X slot interrupts with ACPI and I/O apic - On-board PCI-X GbE and SCSI - ACPI power-off and wakeup with PME# Notes : - Current ACPI is more or less a mess - Interrupts do not route correctly with PIRQ - MP-table is not implemented - Issues with reboots remain (cold and warm) - Many superio devices are disabled by default - Audio codec is not investigated Change-Id: I02d18c83f485a09ada65dde03bcc86e9163f2011 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/303 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Kyösti Mälkki
Patrick Georgi
parent
c5fc7db355
commit
91162705a6
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@ -14,6 +14,8 @@ config VENDOR_ADVANTECH
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bool "Advantech"
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config VENDOR_AMD
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bool "AMD"
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config VENDOR_AOPEN
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bool "AOpen"
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config VENDOR_ARIMA
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bool "Arima"
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config VENDOR_ARTECGROUP
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@ -131,6 +133,7 @@ source "src/mainboard/abit/Kconfig"
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source "src/mainboard/advansus/Kconfig"
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source "src/mainboard/advantech/Kconfig"
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source "src/mainboard/amd/Kconfig"
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source "src/mainboard/aopen/Kconfig"
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source "src/mainboard/arima/Kconfig"
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source "src/mainboard/artecgroup/Kconfig"
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source "src/mainboard/asi/Kconfig"
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@ -0,0 +1,17 @@
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if VENDOR_AOPEN
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choice
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prompt "Mainboard model"
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config BOARD_AOPEN_DXPLPLUSU
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bool "DXPL Plus-U"
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endchoice
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source "src/mainboard/aopen/dxplplusu/Kconfig"
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config MAINBOARD_VENDOR
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string
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default "AOpen"
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endif # VENDOR_AOPEN
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@ -0,0 +1,63 @@
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if BOARD_AOPEN_DXPLPLUSU
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select ARCH_X86
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select CPU_INTEL_SOCKET_MPGA604
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select NORTHBRIDGE_INTEL_E7505
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select SOUTHBRIDGE_INTEL_I82870
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select SOUTHBRIDGE_INTEL_I82801DX
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select SUPERIO_SMSC_LPC47M10X
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select ROMCC
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select HAVE_HARD_RESET
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# select HAVE_PIRQ_TABLE
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# select PIRQ_ROUTE
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select UDELAY_TSC
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select HAVE_ACPI_TABLES
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select BOARD_ROMSIZE_KB_512
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config MAINBOARD_DIR
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string
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default aopen/dxplplusu
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config MAINBOARD_PART_NUMBER
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string
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default "DXPL Plus-U"
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config DCACHE_RAM_BASE
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hex
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default 0xcf000
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config DCACHE_RAM_SIZE
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hex
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default 0x1000
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config IRQ_SLOT_COUNT
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int
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default 12
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config BOARD_HAS_FADT
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bool
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default y
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config LOGICAL_CPUS
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bool
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default n
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config MAX_CPUS
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int
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default 4
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config MAX_PHYSICAL_CPUS
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int
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default 2
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config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
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hex
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default 0x0
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config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
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hex
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default 0x0
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endif # BOARD_AOPEN_DXPLPLUSU
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@ -0,0 +1 @@
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ROMCCFLAGS := -mcpu=p4 -O2
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@ -0,0 +1,86 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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Device (MBRS)
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{
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Name (_HID, EisaId ("PNP0C01"))
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Name (_UID, 0x01)
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Name (MSBF, ResourceTemplate ()
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{
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/* System memory */
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QWordMemory (ResourceProducer, PosDecode, MinFixed,
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MaxNotFixed, Prefetchable, ReadWrite,
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0x0, 0x100000000, 0x400000000, 0x0, 0x0, ,, _Y1C,
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AddressRangeMemory, TypeStatic)
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/* Top Of Low Memory */
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Memory32 (ReadOnly, 0x0, 0x0, 0x1, 0x0, _Y1D)
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/* 640kB who wants more? */
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Memory32Fixed (ReadWrite, 0x0, 0xA0000, )
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/* 64k BIOS bootblock */
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Memory32Fixed (ReadOnly, 0xF0000, 0x10000,)
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/* ISA memory hole 15-16 MB ? */
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/* Memory32Fixed (ReadOnly, 0x100000, 0xF00000,) */
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/* ISA memory hole 14-15 MB ? */
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/* Memory32Fixed (ReadOnly, 0x100000, 0xE00000,) */
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/* Local APIC */
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Memory32Fixed (ReadWrite, 0xFEE00000, 0x00001000,)
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})
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Method (_CRS, 0, NotSerialized)
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{
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CreateQWordField (MSBF, \_SB.MBRS._Y1C._MIN, MEML)
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CreateQWordField (MSBF, \_SB.MBRS._Y1C._MAX, MEMM)
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CreateQWordField (MSBF, \_SB.MBRS._Y1C._LEN, LELM)
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And (\_SB.PCI0.RLAR, 0x03FF, Local1)
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Increment (Local1)
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If (LGreater (Local1, 0x40))
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{
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ShiftLeft (Local1, 0x1A, LELM)
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}
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CreateDWordField (MSBF, \_SB.MBRS._Y1D._MIN, MS00)
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CreateDWordField (MSBF, \_SB.MBRS._Y1D._MAX, MS01)
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CreateDWordField (MSBF, \_SB.MBRS._Y1D._LEN, MEM2)
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And (\_SB.PCI0.TOLM, 0xF800, Local1)
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ShiftRight (Local1, 0x04, Local1)
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Decrement (Local1)
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If (LGreater (Local1, 0x10))
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{
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Subtract (Local1, 0x0F, Local1)
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Store (ShiftLeft (Local1, 0x14), MEM2)
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Store (0x01000000, MS00)
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Store (MS00, MS01)
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}
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Return (MSBF)
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}
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Method (_STA, 0, NotSerialized)
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{
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Return (0x0F)
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}
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}
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@ -0,0 +1,70 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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Name (PBRS, ResourceTemplate ()
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{
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WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
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0x0000, 0x0000, 0x00FF, 0x0000, 0x0100, ,, )
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/* System IO */
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DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x0, 0x0, 0xffff, 0x0000, 0x10000, ,,, TypeStatic)
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IO (Decode16, 0x0CF8, 0x0CF8, 0x08, 0x08, )
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/* Video RAM */
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
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0x00000000, 0x000A0000, 0x000BFFFF,
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0x00000000, 0x00020000, ,,, AddressRangeMemory, TypeStatic)
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/* Video ROM */
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
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0x00000000, 0x000C0000, 0x000C7FFF,
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0x00000000, 0x00008000, ,,, AddressRangeMemory, TypeStatic)
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/* Option ROMs ? */
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
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0x00000000, 0x000C8000, 0x000DFFFF,
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0x00000000, 0x00018000, ,,, AddressRangeMemory, TypeStatic)
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/* Top Of Lowmemory to IOAPIC */
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
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0x00000000, 0x02000000, 0xFEBFFFFF,
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0x00000000, 0xFCC00000, ,, _Y08, AddressRangeMemory, TypeStatic)
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})
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Method (_CRS, 0, NotSerialized)
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{
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/* Top Of Lowmemory to IOAPIC */
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CreateDWordField (PBRS, \_SB.PCI0._Y08._MIN, MEML)
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CreateDWordField (PBRS, \_SB.PCI0._Y08._LEN, LENM)
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And (\_SB.PCI0.TOLM, 0xF800, Local1)
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ShiftRight (Local1, 0x04, Local1)
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ShiftLeft (Local1, 0x14, MEML)
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Subtract (0xFEC00000, MEML, LENM)
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Return (PBRS)
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}
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Method (_STA, 0, NotSerialized)
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{
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Return (0x0F)
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}
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@ -0,0 +1,171 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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Device (USB0)
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{
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Name (_ADR, 0x001D0000)
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Name (_PRW, Package () { 0x03, 0x05 })
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OperationRegion (USBS, PCI_Config, 0x00, 0x0100)
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Field (USBS, ByteAcc, NoLock, Preserve)
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{
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Offset (0xC4), URES, 8
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}
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}
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Device (USB1)
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{
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Name (_ADR, 0x001D0001)
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Name (_PRW, Package () { 0x04, 0x05 })
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OperationRegion (USBS, PCI_Config, 0x00, 0x0100)
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Field (USBS, ByteAcc, NoLock, Preserve)
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{
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Offset (0xC4), URES, 8
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}
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}
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Device (USB2)
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{
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Name (_ADR, 0x001D0002)
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Name (_PRW, Package () { 0x0C, 0x05 })
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OperationRegion (USBS, PCI_Config, 0x00, 0x0100)
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Field (USBS, ByteAcc, NoLock, Preserve)
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{
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Offset (0xC4), URES, 8
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}
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}
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Device (USB3)
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{
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Name (_ADR, 0x001D0007)
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Name (_PRW, Package () { 0x0D, 0x05 }) /* PME_B0_STS any 0:1d or 0:1f device */
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OperationRegion (USBS, PCI_Config, 0x00, 0x0100)
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Field (USBS, ByteAcc, NoLock, Preserve)
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{
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Offset (0xC4), URES, 8
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}
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}
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Device(PCI5)
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{
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Name (_ADR, 0x001E0000)
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Name (_PRW, Package () { 0x0B, 0x05 }) /* PME# _STS */
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Name (_PRT, Package() {
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Package() { 0x0003ffff, 0, 0, 20 },
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Package() { 0x0003ffff, 1, 0, 21 },
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Package() { 0x0003ffff, 2, 0, 22 },
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Package() { 0x0003ffff, 3, 0, 23 },
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})
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}
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Device (ICH0)
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{
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Name (_ADR, 0x001F0000)
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OperationRegion (D310, PCI_Config, 0x00, 0xFF)
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Field (D310, ByteAcc, NoLock, Preserve)
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{
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Offset (0x40), PBAR, 16,
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Offset (0x58), GBAR, 16,
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}
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OperationRegion (ACPI, SystemIO, 0x0400, 0xC0)
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Field (ACPI, ByteAcc, NoLock, Preserve)
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{
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Offset (0x00), PS1L,8, PS1H,8, PE1L,8, PE1H,8,
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Offset (0x28), GS0L,8, GS0H,8, GSPL,8, GSPH,8,
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Offset (0x2C), GE0L,8, GE0H,8, GEPL,8, GEPH,8,
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Offset (0xB8), GPLV,8
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}
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Name (MSBF, ResourceTemplate ()
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{
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/* IOAPIC 0 */
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Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000,)
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IO (Decode16, 0x0, 0x0, 0x80, 0x0, PMIO)
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IO (Decode16, 0x0, 0x0, 0x40, 0x0, GPIO)
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/* 8254 legacy irq */
|
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IO (Decode16, 0x04D0, 0x04D0, 0x02, 0x02,)
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|
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/* reset generator */
|
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IO (Decode16, 0x0092, 0x0092, 0x01, 0x01, )
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})
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Method (_CRS, 0, NotSerialized)
|
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{
|
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CreateWordField (MSBF, \_SB_.PCI0.ICH0.PMIO._MIN, IOA1)
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CreateWordField (MSBF, \_SB_.PCI0.ICH0.PMIO._MAX, IOA2)
|
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CreateByteField (MSBF, \_SB_.PCI0.ICH0.PMIO._LEN, IOAL)
|
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|
||||
Store (PBAR, Local0)
|
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If ( Land(Local0, 0x01) )
|
||||
{
|
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And (Local0, 0xFFFE, Local0)
|
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Store (Local0, IOA1)
|
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Store (Local0, IOA2)
|
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Store (0x80, IOAL)
|
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} Else {
|
||||
Store (0x00, IOAL)
|
||||
}
|
||||
|
||||
CreateWordField (MSBF, \_SB_.PCI0.ICH0.GPIO._MIN, IOS1)
|
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CreateWordField (MSBF, \_SB_.PCI0.ICH0.GPIO._MAX, IOS2)
|
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CreateByteField (MSBF, \_SB_.PCI0.ICH0.GPIO._LEN, IOSL)
|
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|
||||
Store (GBAR, Local0)
|
||||
If ( Land(Local0, 0x01) ) {
|
||||
And (Local0, 0xFFFE, Local0)
|
||||
Store (Local0, IOS1)
|
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Store (Local0, IOS2)
|
||||
Store (0x40, IOSL)
|
||||
} Else {
|
||||
Store (0x00, IOSL)
|
||||
}
|
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Return (MSBF)
|
||||
}
|
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|
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Device (FWH)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C02"))
|
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Name (_UID, 0x01)
|
||||
|
||||
|
||||
Name (MSBG, ResourceTemplate () {
|
||||
Memory32Fixed (ReadOnly, 0xFFF00000, 0x00080000,)
|
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Memory32Fixed (ReadOnly, 0xFFF80000, 0x00080000,)
|
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})
|
||||
|
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Method (_CRS, 0, NotSerialized)
|
||||
{
|
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Return (MSBG)
|
||||
}
|
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}
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|
||||
Device (SMSC)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C02"))
|
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Name (_UID, 0x02)
|
||||
#include "acpi/superio.asl"
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
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|
|
@ -0,0 +1,97 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/* Interrupt routing for PCI 03:xx.x */
|
||||
|
||||
/* I/O APIC id 0x3 */
|
||||
Device(PBIO)
|
||||
{
|
||||
Name (_HID, "ACPI000A")
|
||||
Name (_ADR, 0x001c0000)
|
||||
}
|
||||
|
||||
/* PCI-X bridge */
|
||||
Device(P64B)
|
||||
{
|
||||
Name (_ADR, 0x001d0000)
|
||||
Name (_PRT, Package() {
|
||||
Package() { 0x0002ffff, 0, 0, 24 }, /* PCI-X slot 1 */
|
||||
Package() { 0x0002ffff, 1, 0, 25 },
|
||||
Package() { 0x0002ffff, 2, 0, 26 },
|
||||
Package() { 0x0002ffff, 3, 0, 27 },
|
||||
Package() { 0x0003ffff, 0, 0, 28 }, /* PCI-X slot 2 */
|
||||
Package() { 0x0003ffff, 1, 0, 29 },
|
||||
Package() { 0x0003ffff, 2, 0, 30 },
|
||||
Package() { 0x0003ffff, 3, 0, 31 },
|
||||
Package() { 0x0004ffff, 0, 0, 32 }, /* On-board GbE */
|
||||
})
|
||||
|
||||
Name (_PRW, Package () { 0x0B, 0x05 }) /* PME# _STS */
|
||||
OperationRegion (PBPC, PCI_Config, 0x00, 0xFF)
|
||||
Field (PBPC, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
Offset (0x3E), BCRL, 8, BCRH, 8
|
||||
}
|
||||
|
||||
|
||||
Device (ETH0)
|
||||
{
|
||||
Name (_ADR, 0x00040000)
|
||||
Name (_PRW, Package () { 0x0B, 0x05 }) /* PME# _STS */
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* Interrupt routing for PCI 04:xx.x */
|
||||
|
||||
/* I/O APIC id 0x4 */
|
||||
Device(PAIO)
|
||||
{
|
||||
Name (_HID, "ACPI000A")
|
||||
Name (_ADR, 0x001e0000)
|
||||
}
|
||||
|
||||
/* PCI-X bridge */
|
||||
Device(P64A)
|
||||
{
|
||||
Name (_ADR, 0x001f0000)
|
||||
Name (_PRT, Package() {
|
||||
Package() { 0x0002ffff, 0, 0, 48 }, /* PCI-X slot 3 */
|
||||
Package() { 0x0002ffff, 1, 0, 49 },
|
||||
Package() { 0x0002ffff, 2, 0, 50 },
|
||||
Package() { 0x0002ffff, 3, 0, 51 },
|
||||
Package() { 0x0003ffff, 0, 0, 52 }, /* PCI-X slot 4 */
|
||||
Package() { 0x0003ffff, 1, 0, 53 },
|
||||
Package() { 0x0003ffff, 2, 0, 54 },
|
||||
Package() { 0x0003ffff, 3, 0, 55 },
|
||||
Package() { 0x0004ffff, 0, 0, 54 }, /* On-board SCSI, GSI not 56 ? */
|
||||
Package() { 0x0004ffff, 1, 0, 55 }, /* On-board SCSI, GSI not 57 */
|
||||
})
|
||||
|
||||
Name (_PRW, Package () { 0x0B, 0x05 }) /* PME# _STS */
|
||||
OperationRegion (PBPC, PCI_Config, 0x00, 0xFF)
|
||||
Field (PBPC, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
Offset (0x3E), BCRL, 8, BCRH, 8
|
||||
}
|
||||
|
||||
#include "acpi/scsi.asl"
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
/* Board powers on with button or PME# from on-board GbE wake-on-lan.
|
||||
* Board shuts down to S5/G2. Any other power management is untested.
|
||||
*/
|
||||
|
||||
Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
|
||||
Name (\_S1, Package () { 0x01, 0x01, 0x00, 0x00 })
|
||||
Name (\_S3, Package () { 0x05, 0x05, 0x00, 0x00 })
|
||||
Name (\_S4, Package () { 0x06, 0x06, 0x00, 0x00 })
|
||||
Name (\_S5, Package () { 0x07, 0x07, 0x00, 0x00 })
|
||||
|
||||
Scope (\_GPE)
|
||||
{
|
||||
Method (_L03, 0, NotSerialized)
|
||||
{
|
||||
Notify (\_SB.PCI0.USB0, 0x02)
|
||||
}
|
||||
Method (_L04, 0, NotSerialized)
|
||||
{
|
||||
Notify (\_SB.PCI0.USB1, 0x02)
|
||||
}
|
||||
|
||||
/* WOL header */
|
||||
Method (_L08, 0, NotSerialized)
|
||||
{
|
||||
Notify (\_SB.PCI0.PCI5, 0x02)
|
||||
Notify (\_SB.SLBT, 0x02)
|
||||
}
|
||||
|
||||
/* PME# */
|
||||
Method (_L0B, 0, NotSerialized)
|
||||
{
|
||||
#if 1
|
||||
Notify (\_SB.LID0, 0x02)
|
||||
#else
|
||||
Notify (\_SB.PCI0.HLIB.P64B.ETH0, 0x02)
|
||||
Notify (\_SB.PCI0.HLIB.P64B, 0x02)
|
||||
Notify (\_SB.PCI0.HLIB.P64A, 0x02)
|
||||
#endif
|
||||
}
|
||||
|
||||
Method (_L0C, 0, NotSerialized)
|
||||
{
|
||||
Notify (\_SB.PCI0.USB2, 0x02)
|
||||
}
|
||||
|
||||
/* PME_B0_STS# */
|
||||
Method (_L0D, 0, NotSerialized)
|
||||
{
|
||||
Notify (\_SB.PCI0.USB3, 0x02)
|
||||
}
|
||||
}
|
||||
|
||||
/* Clear power buttons */
|
||||
Method (\_INI, 0, NotSerialized)
|
||||
{
|
||||
Or (\_SB.PCI0.ICH0.PS1H, 0x09, \_SB.PCI0.ICH0.PS1H)
|
||||
Or (\_SB.PCI0.ICH0.PE1H, 0x01, \_SB.PCI0.ICH0.PE1H)
|
||||
}
|
||||
|
||||
/* Prepare To Sleep */
|
||||
Method (\_PTS, 1, NotSerialized)
|
||||
{
|
||||
Or (\_SB.PCI0.ICH0.GS0H, 0x19, \_SB.PCI0.ICH0.GS0H)
|
||||
Or (\_SB.PCI0.ICH0.GS0L, 0x11, \_SB.PCI0.ICH0.GS0L)
|
||||
}
|
||||
|
||||
/* System Wake */
|
||||
Method (\_WAK, 1, NotSerialized)
|
||||
{
|
||||
Or (\_SB.PCI0.ICH0.GS0H, 0x19, \_SB.PCI0.ICH0.GS0H)
|
||||
Or (\_SB.PCI0.ICH0.GS0L, 0x11, \_SB.PCI0.ICH0.GS0L)
|
||||
|
||||
Return ( Package() { 0x0, 0x0 } )
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/* PCI-X devices 04:04.0 and 04:04.1 : AIC-7902W
|
||||
* U320 SCSI dual-channel controller
|
||||
*/
|
||||
|
||||
Device (SCS0)
|
||||
{
|
||||
Name (_ADR, 0x00040000)
|
||||
OperationRegion (SCSC, PCI_Config, 0x00, 0x0100)
|
||||
Field (SCSC, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
Offset (0x2C), SID, 32,
|
||||
Offset (0xE0), PMC, 8,
|
||||
Offset (0xFF), IDW, 8
|
||||
}
|
||||
}
|
||||
|
||||
Device (SCS1)
|
||||
{
|
||||
Name (_ADR, 0x00040001)
|
||||
OperationRegion (SCSC, PCI_Config, 0x00, 0x0100)
|
||||
Field (SCSC, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
Offset (0x2C), SID, 32,
|
||||
Offset (0xE0), PMC, 8,
|
||||
Offset (0xFF), IDW, 8
|
||||
}
|
||||
}
|
||||
|
||||
#if 0
|
||||
/* Set subsystem id for both SCSI devices.
|
||||
* It may require some delay on wake-up before this can be done.
|
||||
*/
|
||||
Method ( )
|
||||
{
|
||||
Or (\_SB.PCI0.HLIB.P64A.SCS0.IDW, 0x01, \_SB.PCI0.HLIB.P64A.SCS0.IDW)
|
||||
Store (0x1106A0A0, \_SB.PCI0.HLIB.P64A.SCS0.SID)
|
||||
And (\_SB.PCI0.HLIB.P64A.SCS0.IDW, 0xFE, \_SB.PCI0.HLIB.P64A.SCS0.IDW)
|
||||
|
||||
Or (\_SB.PCI0.HLIB.P64A.SCS1.IDW, 0x01, \_SB.PCI0.HLIB.P64A.SCS1.IDW)
|
||||
Store (0x1106A0A0, \_SB.PCI0.HLIB.P64A.SCS1.SID)
|
||||
And (\_SB.PCI0.HLIB.P64A.SCS1.IDW, 0xFE, \_SB.PCI0.HLIB.P64A.SCS1.IDW)
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,183 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
/* SuperIO GPIO configuration via logical device 0x0A */
|
||||
|
||||
Name (MSBF, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x0000, 0x0000, 0x01, 0x80, _Y1B)
|
||||
})
|
||||
|
||||
OperationRegion (LPC0, SystemIO, 0x0E00, 0x60)
|
||||
Field (LPC0, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
PME0, 8,
|
||||
Offset (0x02), PME2,8,
|
||||
Offset (0x04), PME4,8,
|
||||
Offset (0x0A), PMEA,8,
|
||||
Offset (0x23),
|
||||
GC10,8, GC11,8, GC12,8, GC13,8, GC14,8, GC15,8, GC16,8, GC17,8,
|
||||
GC20,8, GC21,8, GC22,8, GC23,8, GC24,8, GC25,8, GC26,8, GC27,8,
|
||||
GC30,8, GC31,8, GC32,8, GC33,8, GC34,8, GC35,8, GC36,8, GC37,8,
|
||||
GC40,8, GC41,8, GC42,8, GC43,8,
|
||||
|
||||
Offset (0x3F),
|
||||
GC50,8, GC51,8, GC52,8, GC53,8, GC54,8, GC55,8, GC56,8, GC57,8,
|
||||
GC60,8, GC61,8,
|
||||
|
||||
Offset (0x4B),
|
||||
GP_1,8, GP_2,8, GP_3,8, GP_4,8, GP_5,8, GP_6,8,
|
||||
Offset (0x56), FAN1,8,
|
||||
Offset (0x5D), LED1,8, LED2,8,
|
||||
}
|
||||
|
||||
OperationRegion (SMC1, SystemIO, 0x2E, 0x02)
|
||||
Field (SMC1, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
INDX, 8, DATA, 8
|
||||
}
|
||||
|
||||
IndexField (INDX, DATA, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
Offset (0x07), LDN, 8,
|
||||
Offset (0x22), PWRC, 8,
|
||||
Offset (0x30), ACTR, 8,
|
||||
Offset (0x60),
|
||||
IOAH, 8, IOAL, 8,
|
||||
IOBH, 8, IOBL, 8,
|
||||
|
||||
Offset (0x70), INTR, 8,
|
||||
Offset (0x72), INT1, 8,
|
||||
Offset (0x74), DMCH, 8,
|
||||
Offset (0xB2), SPS1, 8, SPS2, 8,
|
||||
Offset (0xB8), D2TS, 8,
|
||||
Offset (0xF0), OPT1, 8, OPT2, 8, OPT3, 8,
|
||||
Offset (0xF4), WDTC, 8,
|
||||
Offset (0xF6), GP01, 8, GP02, 8, GP04, 8
|
||||
}
|
||||
|
||||
Method (ECFG, 0, NotSerialized)
|
||||
{
|
||||
Store (0x55, INDX)
|
||||
}
|
||||
Method (XCFG, 0, NotSerialized)
|
||||
{
|
||||
Store (0xAA, INDX)
|
||||
}
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
CreateWordField (MSBF, \_SB.PCI0.ICH0.SMSC._Y1B._MIN, IOM1)
|
||||
CreateWordField (MSBF, \_SB.PCI0.ICH0.SMSC._Y1B._MAX, IOM2)
|
||||
CreateByteField (MSBF, \_SB.PCI0.ICH0.SMSC._Y1B._LEN, IOML)
|
||||
|
||||
ECFG ()
|
||||
Store (0x0A, \_SB.PCI0.ICH0.SMSC.LDN)
|
||||
Store (0x00, IOM1)
|
||||
Store (0x00, IOM2)
|
||||
Or (\_SB.PCI0.ICH0.SMSC.IOAH, IOM1, IOM1)
|
||||
ShiftLeft (IOM1, 0x08, IOM1)
|
||||
Or (\_SB.PCI0.ICH0.SMSC.IOAL, IOM1, IOM1)
|
||||
Store (IOM1, IOM2)
|
||||
If (LNotEqual (IOM1, 0x00))
|
||||
{
|
||||
Store (0x80, IOML)
|
||||
}
|
||||
XCFG ()
|
||||
|
||||
Return (MSBF)
|
||||
}
|
||||
|
||||
|
||||
Method (_INI, 0, NotSerialized)
|
||||
{
|
||||
/* GPIO configuration */
|
||||
Store (0x00, GC10)
|
||||
Store (0x81, GC11)
|
||||
Store (0x00, GC17)
|
||||
Store (0x0c, GC21)
|
||||
Store (0x00, GC22)
|
||||
Store (0x04, GC27)
|
||||
Store (0x04, GC30)
|
||||
Store (0x01, GC31)
|
||||
Store (0x01, GC32)
|
||||
Store (0x01, GC33)
|
||||
Store (0x01, GC34) /* GPI password jumper */
|
||||
Store (0x01, GC35) /* GPI scsi enable jumper */
|
||||
#if 1
|
||||
Store (0x01, GC42) /* GPI */
|
||||
#else
|
||||
Store (0x84, GC42) /* nIO_PME */
|
||||
#endif
|
||||
Store (0x86, GC60) /* led 1 */
|
||||
Store (0x81, GC61) /* led 2 ?? */
|
||||
|
||||
/* GPIO initial output levels */
|
||||
Store (GP_1, Local0)
|
||||
And( Local0, 0x7C, Local0)
|
||||
Or ( Local0, 0x81, Local0)
|
||||
Store (Local0, GP_1)
|
||||
|
||||
Store (GP_2, Local0)
|
||||
And( Local0, 0xFE, Local0)
|
||||
Or ( Local0, 0x00, Local0)
|
||||
Store (Local0, GP_2)
|
||||
|
||||
Store (GP_3, Local0)
|
||||
And( Local0, 0x7F, Local0)
|
||||
Or ( Local0, 0x80, Local0)
|
||||
Store (Local0, GP_3)
|
||||
|
||||
Store (GP_4, Local0)
|
||||
And( Local0, 0x7F, Local0)
|
||||
Or ( Local0, 0x00, Local0)
|
||||
Store (Local0, GP_4)
|
||||
|
||||
/* Power Led */
|
||||
Store (LED1, Local0)
|
||||
And( Local0, 0xfc, Local0)
|
||||
Or ( Local0, 0x01, Local0)
|
||||
Store (Local0, LED1)
|
||||
|
||||
}
|
||||
|
||||
Method (MLED, 1, NotSerialized)
|
||||
{
|
||||
If (LEqual (Arg0, 0x00))
|
||||
{
|
||||
Store (0x00, LED1)
|
||||
}
|
||||
|
||||
If (LOr (LEqual (Arg0, 0x01), LEqual (Arg0, 0x02)))
|
||||
{
|
||||
Store (0x01, LED1)
|
||||
}
|
||||
|
||||
If (LEqual (Arg0, 0x03))
|
||||
{
|
||||
Store (0x02, LED1)
|
||||
}
|
||||
|
||||
If (LOr (LEqual (Arg0, 0x04), LEqual (Arg0, 0x05)))
|
||||
{
|
||||
Store (0x03, LED1)
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,163 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Written by Stefan Reinauer <stepan@openbios.org>
|
||||
* (C) 2005 Stefan Reinauer
|
||||
* (C) 2005 Digital Design Corporation
|
||||
*
|
||||
* Ported to Intel XE7501DEVKIT by Agami Aruma
|
||||
* Ported to AOpen DXPL Plus-U by Kyösti Mälkki
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <string.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <assert.h>
|
||||
#include "bus.h"
|
||||
|
||||
extern unsigned char AmlCode[];
|
||||
|
||||
unsigned long acpi_fill_mcfg(unsigned long current)
|
||||
{
|
||||
/* Just a dummy */
|
||||
return current;
|
||||
}
|
||||
|
||||
unsigned long acpi_fill_slit(unsigned long current)
|
||||
{
|
||||
// Not implemented
|
||||
return current;
|
||||
}
|
||||
|
||||
unsigned long acpi_fill_srat(unsigned long current)
|
||||
{
|
||||
// Not implemented
|
||||
return current;
|
||||
}
|
||||
|
||||
unsigned long acpi_fill_madt(unsigned long current)
|
||||
{
|
||||
unsigned int irq_start = 0;
|
||||
device_t dev = 0;
|
||||
struct resource* res = NULL;
|
||||
|
||||
// SJM: Hard-code CPU LAPIC entries for now
|
||||
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0);
|
||||
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 6);
|
||||
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 1);
|
||||
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 7);
|
||||
|
||||
// Southbridge IOAPIC
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_ICH4, 0xfec00000, irq_start);
|
||||
irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
|
||||
|
||||
// P64H2 Bus B IOAPIC
|
||||
dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0));
|
||||
if (!dev)
|
||||
BUG(); // Config.lb error?
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_BUS_B, res->base, irq_start);
|
||||
irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
|
||||
|
||||
// P64H2 Bus A IOAPIC
|
||||
dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0));
|
||||
if (!dev)
|
||||
BUG(); // Config.lb error?
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_BUS_A, res->base, irq_start);
|
||||
irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
|
||||
|
||||
|
||||
// Map ISA IRQ 0 to IRQ 2
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 1, 0, 2, 0);
|
||||
|
||||
// IRQ9 differs from ISA standard - ours is active high, level-triggered
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 0, 9, 9, 0xD);
|
||||
|
||||
return current;
|
||||
}
|
||||
|
||||
#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10)
|
||||
unsigned long write_acpi_tables(unsigned long start)
|
||||
{
|
||||
unsigned long current;
|
||||
acpi_rsdp_t *rsdp;
|
||||
acpi_rsdt_t *rsdt;
|
||||
acpi_madt_t *madt;
|
||||
acpi_facs_t *facs;
|
||||
acpi_fadt_t *fadt;
|
||||
acpi_header_t *dsdt;
|
||||
|
||||
current = start;
|
||||
|
||||
/* Align ACPI tables to 16byte */
|
||||
ALIGN_CURRENT;
|
||||
|
||||
printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
|
||||
|
||||
/* We need at least an RSDP and an RSDT Table */
|
||||
rsdp = (acpi_rsdp_t *) current;
|
||||
current += sizeof(acpi_rsdp_t);
|
||||
ALIGN_CURRENT;
|
||||
rsdt = (acpi_rsdt_t *) current;
|
||||
current += sizeof(acpi_rsdt_t);
|
||||
ALIGN_CURRENT;
|
||||
|
||||
/* clear all table memory */
|
||||
memset((void *)start, 0, current - start);
|
||||
|
||||
acpi_write_rsdp(rsdp, rsdt, NULL);
|
||||
acpi_write_rsdt(rsdt);
|
||||
|
||||
/*
|
||||
* We explicitly add these tables later on:
|
||||
*/
|
||||
printk(BIOS_DEBUG, "ACPI: * FADT\n");
|
||||
fadt = (acpi_fadt_t *) current;
|
||||
current += sizeof(acpi_fadt_t);
|
||||
ALIGN_CURRENT;
|
||||
|
||||
printk(BIOS_DEBUG, "ACPI: * FACS\n");
|
||||
facs = (acpi_facs_t *) current;
|
||||
current += sizeof(acpi_facs_t);
|
||||
ALIGN_CURRENT;
|
||||
acpi_create_facs(facs);
|
||||
|
||||
dsdt = (acpi_header_t *)current;
|
||||
memcpy(dsdt,(void *)AmlCode, sizeof(acpi_header_t));
|
||||
current += dsdt->length;
|
||||
ALIGN_CURRENT;
|
||||
memcpy(dsdt,(void *)AmlCode, dsdt->length);
|
||||
dsdt->checksum = 0;
|
||||
dsdt->checksum = acpi_checksum((void *)dsdt,dsdt->length);
|
||||
printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length);
|
||||
|
||||
acpi_create_fadt(fadt,facs,dsdt);
|
||||
acpi_add_table(rsdp,fadt);
|
||||
|
||||
printk(BIOS_DEBUG, "ACPI: * MADT\n");
|
||||
madt = (acpi_madt_t *) current;
|
||||
acpi_create_madt(madt);
|
||||
current+=madt->header.length;
|
||||
ALIGN_CURRENT;
|
||||
acpi_add_table(rsdp,madt);
|
||||
|
||||
printk(BIOS_INFO, "ACPI: done.\n");
|
||||
return current;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef DXPLPLUSU_BUS_H_INCLUDED
|
||||
#define DXPLPLUSU_BUS_H_INCLUDED
|
||||
|
||||
// These were determined by seeing how coreboot enumerates the various
|
||||
// PCI (and PCI-like) buses on the board.
|
||||
|
||||
#define PCI_BUS_ROOT 0
|
||||
#define PCI_BUS_AGP 1 // AGP
|
||||
#define PCI_BUS_E7501_HI_B 2 // P64H2#1
|
||||
#define PCI_BUS_P64H2_B 3 // P64H2#1 bus B
|
||||
#define PCI_BUS_P64H2_A 4 // P64H2#1 bus A
|
||||
#define PCI_BUS_ICH4 5 // ICH4
|
||||
|
||||
// IOAPIC addresses determined by coreboot enumeration.
|
||||
// Someday add functions to get APIC IDs and versions from the chips themselves.
|
||||
|
||||
#define IOAPIC_ICH4 2
|
||||
#define IOAPIC_P64H2_BUS_B 3 // IOAPIC 3 at 02:1c.0 MBAR = fe300000 DataAddr = fe300010
|
||||
#define IOAPIC_P64H2_BUS_A 4 // IOAPIC 4 at 02:1e.0 MBAR = fe301000 DataAddr = fe301010
|
||||
|
||||
#define INTEL_IOAPIC_NUM_INTERRUPTS 24 // Both ICH-4 and P64-H2
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
extern struct chip_operations mainboard_ops;
|
||||
|
||||
struct mainboard_config {
|
||||
};
|
||||
|
|
@ -0,0 +1,87 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki@gmail.com>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or
|
||||
## modify it under the terms of the GNU General Public License as
|
||||
## published by the Free Software Foundation; version 2 of
|
||||
## the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
## MA 02110-1301 USA
|
||||
##
|
||||
|
||||
chip northbridge/intel/e7505
|
||||
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/intel/socket_mPGA604
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
|
||||
device pci_domain 0 on
|
||||
device pci 0.0 on end # Chipset host controller
|
||||
device pci 0.1 on end # Host RASUM controller
|
||||
device pci 2.0 on # Hub interface B
|
||||
chip southbridge/intel/i82870 # P64H2
|
||||
device pci 1c.0 on end # IOAPIC - bus B
|
||||
device pci 1d.0 on end # Hub to PCI-B bridge
|
||||
device pci 1e.0 on end # IOAPIC - bus A
|
||||
device pci 1f.0 on end # Hub to PCI-A bridge
|
||||
end
|
||||
end
|
||||
device pci 4.0 off end # (undocumented)
|
||||
device pci 6.0 off end # (undocumented)
|
||||
chip southbridge/intel/i82801dx
|
||||
device pci 1d.0 on end # USB UHCI
|
||||
device pci 1d.1 on end # USB UHCI
|
||||
device pci 1d.2 on end # USB UHCI
|
||||
device pci 1d.7 on end # USB EHCI
|
||||
device pci 1e.0 on # Hub to PCI bridge
|
||||
device pci 2.0 off end
|
||||
end
|
||||
device pci 1f.0 on # LPC bridge
|
||||
chip superio/smsc/lpc47m10x
|
||||
device pnp 2e.0 off # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.3 off # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.4 on # Com1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.5 off # Com2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.7 off # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1 # Keyboard interrupt
|
||||
irq 0x72 = 12 # Mouse interrupt
|
||||
end
|
||||
device pnp 2e.a on # ACPI
|
||||
io 0x60 = 0x0e00
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 1f.1 on end # IDE
|
||||
device pci 1f.3 on end # SMBus
|
||||
device pci 1f.5 on end # AC97 Audio
|
||||
device pci 1f.6 off end # AC97 Modem
|
||||
end # SB
|
||||
end # PCI_DOMAIN
|
||||
end
|
||||
|
|
@ -0,0 +1,113 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
DefinitionBlock(
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
0x04, // DSDT revision: ACPI v4.0
|
||||
"COREv4", // OEM id
|
||||
"COREBOOT", // OEM table id
|
||||
0x20111103 // OEM revision
|
||||
) {
|
||||
|
||||
Scope(\_SB)
|
||||
{
|
||||
Device(PCI0) {
|
||||
Name (_HID, EISAID("PNP0A03"))
|
||||
Name (_ADR, 0x00)
|
||||
Name (_PRT, Package() {
|
||||
Package() { 0x001dffff, 0, 0, 16 },
|
||||
Package() { 0x001dffff, 1, 0, 19 },
|
||||
Package() { 0x001dffff, 2, 0, 18 },
|
||||
Package() { 0x001dffff, 3, 0, 23 },
|
||||
Package() { 0x001fffff, 0, 0, 18 },
|
||||
Package() { 0x001fffff, 1, 0, 17 },
|
||||
})
|
||||
|
||||
#include "acpi/e7505_sec.asl"
|
||||
|
||||
OperationRegion (I750, PCI_Config, 0x00, 0x0100)
|
||||
Field (I750, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
Offset (0xC4),
|
||||
TOLM, 16, /* Top of Low Memory */
|
||||
RBAR, 16, /* REMAP_BASE */
|
||||
RLAR, 16 /* REMAP_LIMIT */
|
||||
}
|
||||
}
|
||||
|
||||
#include "acpi/e7505_pri.asl"
|
||||
|
||||
|
||||
Device (PWBT)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C0C"))
|
||||
Name (_PRW, Package () { 0x08, 0x05 })
|
||||
}
|
||||
|
||||
Device (SLBT)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C0E"))
|
||||
Name (_PRW, Package () { 0x0B, 0x05 })
|
||||
}
|
||||
|
||||
Device (LID0)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C0D"))
|
||||
Name (_PRW, Package () { 0x0B, 0x05 })
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
Scope(\_SB.PCI0)
|
||||
{
|
||||
|
||||
Device(PCI1)
|
||||
{
|
||||
Name (_ADR, 0x00010000)
|
||||
Name (_PRT, Package() {
|
||||
Package() { 0x0000ffff, 0, 0, 16 },
|
||||
Package() { 0x0000ffff, 1, 0, 17 },
|
||||
})
|
||||
}
|
||||
|
||||
Device(HLIB)
|
||||
{
|
||||
Name (_ADR, 0x00020000)
|
||||
Name (_PRT, Package() {
|
||||
Package() { 0x001dffff, 0, 0, 18 },
|
||||
Package() { 0x001dffff, 1, 0, 18 },
|
||||
Package() { 0x001dffff, 2, 0, 18 },
|
||||
Package() { 0x001dffff, 3, 0, 18 },
|
||||
Package() { 0x001fffff, 0, 0, 18 },
|
||||
Package() { 0x001fffff, 1, 0, 18 },
|
||||
Package() { 0x001fffff, 2, 0, 18 },
|
||||
Package() { 0x001fffff, 3, 0, 18 },
|
||||
})
|
||||
|
||||
#include "acpi/p64h2.asl"
|
||||
}
|
||||
|
||||
#include "acpi/i82801db.asl"
|
||||
}
|
||||
|
||||
#include "acpi/power.asl"
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,166 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include <device/pci.h>
|
||||
#include <arch/acpi.h>
|
||||
|
||||
/* FIXME: This needs to go into a separate .h file
|
||||
* to be included by the ich7 smi handler, ich7 smi init
|
||||
* code and the mainboard fadt.
|
||||
*/
|
||||
#define APM_CNT 0x0 /* ACPI mode only */
|
||||
#define CST_CONTROL 0x85
|
||||
#define PST_CONTROL 0x0
|
||||
#define ACPI_DISABLE 0xAA
|
||||
#define ACPI_ENABLE 0x55
|
||||
#define S4_BIOS 0x77
|
||||
#define GNVS_UPDATE 0xea
|
||||
|
||||
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
|
||||
{
|
||||
acpi_header_t *header = &(fadt->header);
|
||||
u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe;
|
||||
|
||||
memset((void *) fadt, 0, sizeof(acpi_fadt_t));
|
||||
memcpy(header->signature, "FACP", 4);
|
||||
header->length = sizeof(acpi_fadt_t);
|
||||
header->revision = 4;
|
||||
memcpy(header->oem_id, OEM_ID, 6);
|
||||
memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
|
||||
memcpy(header->asl_compiler_id, ASLC, 4);
|
||||
header->asl_compiler_revision = 1;
|
||||
|
||||
fadt->firmware_ctrl = (unsigned long) facs;
|
||||
fadt->dsdt = (unsigned long) dsdt;
|
||||
fadt->model = 1;
|
||||
fadt->preferred_pm_profile = 0; /* PM_MOBILE; */
|
||||
|
||||
fadt->sci_int = 0x9;
|
||||
fadt->smi_cmd = APM_CNT;
|
||||
fadt->acpi_enable = ACPI_ENABLE;
|
||||
fadt->acpi_disable = ACPI_DISABLE;
|
||||
fadt->s4bios_req = S4_BIOS;
|
||||
fadt->pstate_cnt = PST_CONTROL;
|
||||
|
||||
fadt->pm1a_evt_blk = pmbase;
|
||||
fadt->pm1b_evt_blk = 0x0;
|
||||
fadt->pm1a_cnt_blk = pmbase + 0x4;
|
||||
fadt->pm1b_cnt_blk = 0x0;
|
||||
fadt->pm2_cnt_blk = 0x0;
|
||||
fadt->pm_tmr_blk = pmbase + 0x8;
|
||||
fadt->gpe0_blk = pmbase + 0x28;
|
||||
fadt->gpe1_blk = 0;
|
||||
|
||||
fadt->pm1_evt_len = 4;
|
||||
fadt->pm1_cnt_len = 2;
|
||||
// XXX: pm2_cnt_len is probably wrong. find out right value (hint: it's != 0)
|
||||
fadt->pm2_cnt_len = 0;
|
||||
fadt->pm_tmr_len = 4;
|
||||
fadt->gpe0_blk_len = 8;
|
||||
fadt->gpe1_blk_len = 0;
|
||||
fadt->gpe1_base = 0;
|
||||
fadt->cst_cnt = 0; /* CST_CONTROL; */
|
||||
fadt->p_lvl2_lat = 1;
|
||||
fadt->p_lvl3_lat = 85;
|
||||
fadt->flush_size = 1024;
|
||||
fadt->flush_stride = 16;
|
||||
fadt->duty_offset = 1;
|
||||
fadt->duty_width = 0;
|
||||
fadt->day_alrm = 0xd;
|
||||
fadt->mon_alrm = 0x00;
|
||||
fadt->century = 0x00;
|
||||
fadt->iapc_boot_arch = 0x03;
|
||||
|
||||
fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
|
||||
ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
|
||||
ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
|
||||
|
||||
fadt->reset_reg.space_id = 0;
|
||||
fadt->reset_reg.bit_width = 0;
|
||||
fadt->reset_reg.bit_offset = 0;
|
||||
fadt->reset_reg.resv = 0;
|
||||
fadt->reset_reg.addrl = 0x0;
|
||||
fadt->reset_reg.addrh = 0x0;
|
||||
|
||||
fadt->reset_value = 0;
|
||||
fadt->x_firmware_ctl_l = (unsigned long)facs;
|
||||
fadt->x_firmware_ctl_h = 0;
|
||||
fadt->x_dsdt_l = (unsigned long)dsdt;
|
||||
fadt->x_dsdt_h = 0;
|
||||
|
||||
fadt->x_pm1a_evt_blk.space_id = 1;
|
||||
fadt->x_pm1a_evt_blk.bit_width = 32;
|
||||
fadt->x_pm1a_evt_blk.bit_offset = 0;
|
||||
fadt->x_pm1a_evt_blk.resv = 0;
|
||||
fadt->x_pm1a_evt_blk.addrl = pmbase;
|
||||
fadt->x_pm1a_evt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1b_evt_blk.space_id = 1;
|
||||
fadt->x_pm1b_evt_blk.bit_width = 0;
|
||||
fadt->x_pm1b_evt_blk.bit_offset = 0;
|
||||
fadt->x_pm1b_evt_blk.resv = 0;
|
||||
fadt->x_pm1b_evt_blk.addrl = 0x0;
|
||||
fadt->x_pm1b_evt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1a_cnt_blk.space_id = 1;
|
||||
fadt->x_pm1a_cnt_blk.bit_width = 16;
|
||||
fadt->x_pm1a_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm1a_cnt_blk.resv = 0;
|
||||
fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
|
||||
fadt->x_pm1a_cnt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1b_cnt_blk.space_id = 1;
|
||||
fadt->x_pm1b_cnt_blk.bit_width = 0;
|
||||
fadt->x_pm1b_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm1b_cnt_blk.resv = 0;
|
||||
fadt->x_pm1b_cnt_blk.addrl = 0x0;
|
||||
fadt->x_pm1b_cnt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm2_cnt_blk.space_id = 1;
|
||||
fadt->x_pm2_cnt_blk.bit_width = 0;
|
||||
fadt->x_pm2_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm2_cnt_blk.resv = 0;
|
||||
fadt->x_pm2_cnt_blk.addrl = 0x0;
|
||||
fadt->x_pm2_cnt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm_tmr_blk.space_id = 1;
|
||||
fadt->x_pm_tmr_blk.bit_width = 32;
|
||||
fadt->x_pm_tmr_blk.bit_offset = 0;
|
||||
fadt->x_pm_tmr_blk.resv = 0;
|
||||
fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
|
||||
fadt->x_pm_tmr_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_gpe0_blk.space_id = 1;
|
||||
fadt->x_gpe0_blk.bit_width = 64;
|
||||
fadt->x_gpe0_blk.bit_offset = 0;
|
||||
fadt->x_gpe0_blk.resv = 0;
|
||||
fadt->x_gpe0_blk.addrl = pmbase + 0x28;
|
||||
fadt->x_gpe0_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_gpe1_blk.space_id = 1;
|
||||
fadt->x_gpe1_blk.bit_width = 0;
|
||||
fadt->x_gpe1_blk.bit_offset = 0;
|
||||
fadt->x_gpe1_blk.resv = 0;
|
||||
fadt->x_gpe1_blk.addrl = 0x0;
|
||||
fadt->x_gpe1_blk.addrh = 0x0;
|
||||
|
||||
header->checksum =
|
||||
acpi_checksum((void *) fadt, header->length);
|
||||
}
|
||||
|
|
@ -0,0 +1,76 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include "bus.h"
|
||||
|
||||
#define UNUSED_INTERRUPT {0, 0}
|
||||
#define PIRQ_A 0x60
|
||||
#define PIRQ_B 0x61
|
||||
#define PIRQ_C 0x62
|
||||
#define PIRQ_D 0x63
|
||||
#define PIRQ_E 0x68
|
||||
#define PIRQ_F 0x69
|
||||
#define PIRQ_G 0x6A
|
||||
#define PIRQ_H 0x6B
|
||||
|
||||
const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE,
|
||||
PIRQ_VERSION,
|
||||
32 + 16 * CONFIG_IRQ_SLOT_COUNT, // Size of this struct in bytes
|
||||
0, // PCI bus number on which the interrupt router resides
|
||||
PCI_DEVFN(31, 0), // PCI device/function number of the interrupt router
|
||||
0, // PCI-exclusive IRQ bitmap
|
||||
PCI_VENDOR_ID_INTEL, // Vendor ID of compatible PCI interrupt router
|
||||
PCI_DEVICE_ID_INTEL_82801DB_LPC, // Device ID of compatible PCI interrupt router
|
||||
0, // Additional miniport information
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, // Reserved, must be zero
|
||||
0xB1, // Checksum of the entire structure (causes 8-bit sum == 0)
|
||||
{
|
||||
// NOTE: For 82801, a nonzero link value is a pointer to a PIRQ[n]_ROUT register in PCI configuration space
|
||||
// This was determined from linux-2.6.11/arch/i386/pci/irq.c
|
||||
// bitmap of 0xdcf8 == routable to IRQ3-IRQ7, IRQ10-IRQ12, or IRQ14-IRQ15
|
||||
// ICH-3 doesn't allow SERIRQ or PCI message to generate IRQ0, IRQ2, IRQ8, or IRQ13
|
||||
// Not sure why IRQ9 isn't routable (inherited from Tyan S2735)
|
||||
|
||||
// INTA# INTB# INTC# INTD#
|
||||
// bus, device # {link , bitmap}, {link , bitmap}, {link , bitmap}, {link , bitmap}, slot, rfu
|
||||
|
||||
{PCI_BUS_ROOT, PCI_DEVFN(31, 0), {{PIRQ_C, 0xdcf8}, {PIRQ_B, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // IDE / SMBus
|
||||
{PCI_BUS_ROOT, PCI_DEVFN(29, 0), {{PIRQ_A, 0xdcf8}, {PIRQ_D, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_H, 0xdcf8}}, 0, 0}, // USB 1.1
|
||||
|
||||
{PCI_BUS_P64H2_B, PCI_DEVFN(2, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0},
|
||||
{PCI_BUS_P64H2_B, PCI_DEVFN(3, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0},
|
||||
{PCI_BUS_P64H2_B, PCI_DEVFN(4, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, // GbE
|
||||
|
||||
{PCI_BUS_P64H2_A, PCI_DEVFN(2, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0},
|
||||
{PCI_BUS_P64H2_A, PCI_DEVFN(3, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0},
|
||||
{PCI_BUS_P64H2_A, PCI_DEVFN(4, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, // SCSI
|
||||
|
||||
{PCI_BUS_ICH4, PCI_DEVFN(3, 0), {{PIRQ_E, 0xdcf8}, {PIRQ_F, 0xdcf8}, {PIRQ_G, 0xdcf8}, {PIRQ_H, 0xdcf8}}, 0, 0}, // 32-bit slot
|
||||
|
||||
}
|
||||
};
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
return copy_pirq_routing_table(addr);
|
||||
}
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
#include <device/device.h>
|
||||
#include "chip.h"
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
CHIP_NAME("AOpen DXPL Plus-U Mainboard")
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,103 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <arch/romcc_io.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <arch/cpu.h>
|
||||
#include <stdlib.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <console/console.h>
|
||||
|
||||
#include "southbridge/intel/i82801dx/i82801dx.h"
|
||||
#include "southbridge/intel/i82801dx/early_smbus.c"
|
||||
#include "southbridge/intel/i82801dx/reset.c"
|
||||
#include "northbridge/intel/e7505/raminit.h"
|
||||
#include "northbridge/intel/e7505/debug.c"
|
||||
#include "superio/smsc/lpc47m10x/early_serial.c"
|
||||
|
||||
#if !CONFIG_CACHE_AS_RAM
|
||||
#include "cpu/x86/lapic/boot_cpu.c"
|
||||
#include "cpu/x86/mtrr/earlymtrr.c"
|
||||
#endif
|
||||
#include "cpu/x86/bist.h"
|
||||
|
||||
#include <spd.h>
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, LPC47M10X2_SP1)
|
||||
|
||||
static inline int spd_read_byte(unsigned device, unsigned address)
|
||||
{
|
||||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
/* Cache-As-Ram compiles for this board, but with the CPUs I have,
|
||||
* it halts on boot while in Local Apic ID negotiation.
|
||||
*/
|
||||
|
||||
#if CONFIG_CACHE_AS_RAM
|
||||
#define BOARD_MAIN(x) void main(x)
|
||||
#define early_mtrr_init() do {} while (0)
|
||||
#else
|
||||
#define BOARD_MAIN(x) static void main(x)
|
||||
#endif
|
||||
|
||||
#include "northbridge/intel/e7505/raminit.c"
|
||||
#include "northbridge/intel/e7505/reset_test.c"
|
||||
#include "lib/generic_sdram.c"
|
||||
|
||||
// This function MUST appear last (ROMCC limitation)
|
||||
BOARD_MAIN(unsigned long bist)
|
||||
{
|
||||
static const struct mem_controller memctrl[] = {
|
||||
{
|
||||
.d0 = PCI_DEV(0, 0, 0),
|
||||
.d0f1 = PCI_DEV(0, 0, 1),
|
||||
.channel0 = { 0x50, 0x52, 0, 0 },
|
||||
.channel1 = { 0x51, 0x53, 0, 0 },
|
||||
},
|
||||
};
|
||||
|
||||
if (bist == 0) {
|
||||
// Skip this if there was a built in self test failure
|
||||
early_mtrr_init();
|
||||
enable_lapic();
|
||||
}
|
||||
|
||||
// Get the serial port running and print a welcome banner
|
||||
lpc47m10x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
console_init();
|
||||
|
||||
// Halt if there was a built in self test failure
|
||||
report_bist_failure(bist);
|
||||
|
||||
// If this is a warm boot, some initialization can be skipped
|
||||
if (!bios_reset_detected()) {
|
||||
enable_smbus();
|
||||
sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
|
||||
}
|
||||
|
||||
// NOTE: ROMCC dies with an internal compiler error
|
||||
// if the following line is removed.
|
||||
print_debug("SDRAM is up.\r\n");
|
||||
|
||||
}
|
||||
Loading…
Reference in New Issue