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soc/intel/apollolake: Make eMMC max speed configurable

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The eMMC maximum speed is set to HS400 mode per default. To increase the
lifetime of the circuit, it is necessary to reduce the eMMC speed.

Change-Id: I6fa5eb56a0593e24269ef143645c506232879889
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/28282
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Mario Scheithauer 2018-08-23 11:39:19 +02:00 committed by Patrick Georgi
parent 31a4700ce9
commit 9116eb660e
2 changed files with 7 additions and 2 deletions
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4
src/soc/intel/apollolake/chip.c
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@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2015 - 2017 Intel Corp.
* Copyright (C) 2017 Siemens AG
* Copyright (C) 2017 - 2018 Siemens AG
* (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
* (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
*
@ -616,6 +616,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
silconfig->EmmcRxStrobeCntl = cfg->emmc_rx_strobe_cntl;
if (cfg->emmc_rx_cmd_data_cntl2 != 0)
silconfig->EmmcRxCmdDataCntl2 = cfg->emmc_rx_cmd_data_cntl2;
if (cfg->emmc_host_max_speed != 0)
silconfig->eMMCHostMaxSpeed = cfg->emmc_host_max_speed;
silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable;

5
src/soc/intel/apollolake/chip.h
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@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Intel Corp.
* Copyright (C) 2017 Siemens AG
* Copyright (C) 2017 - 2018 Siemens AG
* (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
*
* This program is free software; you can redistribute it and/or modify
@ -93,6 +93,9 @@ struct soc_intel_apollolake_config {
*/
uint32_t emmc_rx_cmd_data_cntl2;
/* Select the eMMC max speed allowed. */
uint8_t emmc_host_max_speed;
/* Specifies on which IRQ the SCI will internally appear. */
uint8_t sci_irq;