util/mb/google/tmpl/puff: Update DPTF to the new implementation
Apply the change in CB:44905 to the puff template, moving DPTF policies from static ASL files into the new SSDT-based DPTF implementation. BUG=b:158986928 BRANCH=puff TEST=None Change-Id: I601fd4c6aeaa3afee0f7fd9d13376f2fffd6d793 Signed-off-by: Sam McNally <sammc@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <puff/acpi/dptf.asl>
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@ -204,6 +204,71 @@ chip soc/intel/cannonlake
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register "sata_port[1].TxGen3DeEmph" = "0x20"
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device domain 0 on
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device pci 04.0 on
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chip drivers/intel/dptf
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## Active Policy
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register "policies.active[0]" = "{.target=DPTF_CPU,
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.thresholds={TEMP_PCT(90, 85),
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TEMP_PCT(85, 75),
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TEMP_PCT(80, 65),
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TEMP_PCT(75, 55),
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TEMP_PCT(70, 45),}}"
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register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0,
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.thresholds={TEMP_PCT(50, 85),
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TEMP_PCT(47, 75),
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TEMP_PCT(45, 65),
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TEMP_PCT(42, 55),
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TEMP_PCT(39, 45),}}"
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## Passive Policy
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register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 93, 5000)"
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register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)"
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## Critical Policy
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register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)"
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register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)"
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## Power Limits Control
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# PL1 is fixed at 15W, avg over 28-32s interval
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# 25-64W PL2 in 1000mW increments, avg over 28-32s interval
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register "controls.power_limits.pl1" = "{
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.min_power = 15000,
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.max_power = 15000,
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.time_window_min = 28 * MSECS_PER_SEC,
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.time_window_max = 32 * MSECS_PER_SEC,
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.granularity = 200,}"
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register "controls.power_limits.pl2" = "{
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.min_power = 25000,
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.max_power = 64000,
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.time_window_min = 28 * MSECS_PER_SEC,
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.time_window_max = 32 * MSECS_PER_SEC,
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.granularity = 1000,}"
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## Charger Performance Control (Control, mA)
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register "controls.charger_perf[0]" = "{ 255, 1700 }"
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register "controls.charger_perf[1]" = "{ 24, 1500 }"
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register "controls.charger_perf[2]" = "{ 16, 1000 }"
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register "controls.charger_perf[3]" = "{ 8, 500 }"
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## Fan Performance Control (Percent, Speed, Noise, Power)
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register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }"
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register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }"
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register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }"
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register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }"
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register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }"
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register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }"
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register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }"
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register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }"
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register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }"
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register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }"
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# Fan options
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register "options.fan.fine_grained_control" = "1"
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register "options.fan.step_size" = "2"
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device generic 0 on end
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end
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end # DPTF 0x1903
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device pci 14.0 on
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chip drivers/usb/acpi
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device usb 0.0 on
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