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mb/google/brya/var/taeko: Fix PLD group order 

Ensure USB-C ports' _PLD group numbers appear in order.

get_usb_port_references in src/ec/google/chromeec/ec_acpi.c uses group
token to match with the Type-C port number.

BUG=b:216490477
TEST=build coreboot and system boot into OS.
BRANCH=firmware-brya-14505.B

Change-Id: I5c0395d33ee47ab1c7d45f33d6afb063b8263836
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75572
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Won Chung 2023-06-01 00:27:50 +00:00 committed by Martin L Roth
parent 7906d0e122
commit 912edb4f0f
1 changed files with 2 additions and 2 deletions
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4
src/mainboard/google/brya/variants/taeko/overridetree.cb
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@ -599,7 +599,7 @@ chip soc/intel/alderlake
register "desc" = ""USB3 Type-C Port C1 (DB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))"
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
register "usb_lpm_incapable" = "true"
device ref tcss_usb3_port3 on
probe DB_USB DB_USB3_NO_A
@ -623,7 +623,7 @@ chip soc/intel/alderlake
register "desc" = ""USB2 Type-C Port C1 (DB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))"
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
device ref usb2_port3 on
probe DB_USB DB_USB3_NO_A
probe DB_USB DB_USB3_1C_1A