From 9138eee4f7ed304a27fcb0028dd8865d79537374 Mon Sep 17 00:00:00 2001
From: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Date: Mon, 20 Apr 2020 15:20:55 +0800
Subject: [PATCH] mb/google/deltaur: Correct SPD SMBus address

SMBus uses 7-bits address, change it from 8-bits to 7-bits.

BUG=b:151702387
TEST=Check Memory SPD data is correct in console log.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I1720b4d6aa0bc785ad86234b3523bb0676ec5c82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
---
 src/mainboard/google/deltaur/variants/deltan/memory.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/deltaur/variants/deltan/memory.c b/src/mainboard/google/deltaur/variants/deltan/memory.c
index d51ba70431..0c5873f056 100644
--- a/src/mainboard/google/deltaur/variants/deltan/memory.c
+++ b/src/mainboard/google/deltaur/variants/deltan/memory.c
@@ -48,9 +48,9 @@ void variant_memory_init(FSP_M_CONFIG *mem_cfg)
 {
 	const struct spd_info spd_info = {
 		.topology = SODIMM,
-		.smbus_info[0] = {.addr_dimm0 = 0xa0,
+		.smbus_info[0] = {.addr_dimm0 = 0x50,
 				  .addr_dimm1 = 0 },
-		.smbus_info[1] = {.addr_dimm0 = 0xa4,
+		.smbus_info[1] = {.addr_dimm0 = 0x52,
 				  .addr_dimm1 = 0 },
 	};
 	const bool half_populated = false;