soc/amd/cezanne/smihandler: implement S3 entry SMI handler
Since the support for the GSMI ELOG isn't implemented in the SMI handler yet, the corresponding code isn't added to fch_slp_typ_handler in this patch. BUG=b:181766974 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia27b2486dde1a373607ce895a975e873d9026ba1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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@ -9,8 +9,11 @@
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#include <arch/hlt.h>
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#include <arch/io.h>
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#include <console/console.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/smm.h>
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#include <soc/smi.h>
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#include <soc/smu.h>
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#include <soc/southbridge.h>
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#include <types.h>
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static void fch_apmc_smi_handler(void)
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@ -34,8 +37,9 @@ static void fch_apmc_smi_handler(void)
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static void fch_slp_typ_handler(void)
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{
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uint32_t pci_ctrl;
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uint16_t pm1cnt;
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uint8_t slp_typ;
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uint8_t slp_typ, rst_ctrl;
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/* Figure out SLP_TYP */
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pm1cnt = acpi_read16(MMIO_ACPI_PM1_CNT_BLK);
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@ -64,6 +68,24 @@ static void fch_slp_typ_handler(void)
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}
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if (slp_typ >= ACPI_S3) {
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wbinvd();
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clear_all_smi_status();
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/* Do not send SMI before AcpiPm1CntBlkx00[SlpTyp] */
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pci_ctrl = pm_read32(PM_PCI_CTRL);
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pci_ctrl &= ~FORCE_SLPSTATE_RETRY;
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pm_write32(PM_PCI_CTRL, pci_ctrl);
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/* Enable SlpTyp */
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rst_ctrl = pm_read8(PM_RST_CTRL1);
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rst_ctrl |= SLPTYPE_CONTROL_EN;
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pm_write8(PM_RST_CTRL1, rst_ctrl);
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if (slp_typ == ACPI_S3)
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psp_notify_sx_info(ACPI_S3);
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smu_sx_entry(); /* Leave SlpTypeEn clear, SMU will set */
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printk(BIOS_ERR, "Error: System did not go to sleep\n");
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hlt();
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}
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