soc/intel: Select GMA v2 for ADL, MTL, TGL to reflect port/pipe defs

Intel GFX IP TRANS_DDI_FUNC_CTL register bit definitions have changed
since Tiger Lake.

This register is used to map ports and pipes to display controllers,
so reflecting the correct status is important for detecting physical
display end point devices.

This patch ensures that ADL, MTL, and TGL SoCs choose GMA version 2 to
properly reflect the updated port and pipe register definitions.

BUG=b:299137940
TEST=Build and boot google/rex successfully.

Change-Id: Ie2082747d18a5f136f410b1019be4d6c801617b1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>

src/soc/intel/alderlake/Kconfig

@@ -29,6 +29,7 @@ config SOC_INTEL_ALDERLAKE
 	select INTEL_GMA_ACPI
 	select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
 	select INTEL_GMA_OPREGION_2_1
+	select INTEL_GMA_VERSION_2
 	select INTEL_TXT_LIB
 	select MP_SERVICES_PPI_V2
 	select MRC_SETTINGS_PROTECT

src/soc/intel/meteorlake/Kconfig

@@ -31,6 +31,7 @@ config SOC_INTEL_METEORLAKE
 	select INTEL_GMA_ACPI
 	select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
 	select INTEL_GMA_OPREGION_2_1
+	select INTEL_GMA_VERSION_2
 	select IOAPIC
 	select MICROCODE_BLOB_UNDISCLOSED
 	select MP_SERVICES_PPI_V2

src/soc/intel/tigerlake/Kconfig

@@ -29,6 +29,7 @@ config SOC_INTEL_TIGERLAKE
 	select SF_MASK_2WAYS_PER_BIT if INTEL_CAR_NEM_ENHANCED
 	select INTEL_GMA_ACPI
 	select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
+	select INTEL_GMA_VERSION_2
 	select MP_SERVICES_PPI_V1
 	select MRC_SETTINGS_PROTECT
 	select PARALLEL_MP_AP_WORK