diff --git a/src/mainboard/google/kahlee/chromeos.c b/src/mainboard/google/kahlee/chromeos.c
index 4112db5677..156614bbb8 100644
--- a/src/mainboard/google/kahlee/chromeos.c
+++ b/src/mainboard/google/kahlee/chromeos.c
@@ -18,7 +18,7 @@
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <boot/coreboot_tables.h>
 #include <console/console.h>
-#include <soc/gpio.h>
+#include <gpio.h>
 
 /* SPI Write protect */
 #define CROS_WP_GPIO	GPIO_122
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index f1f2c12e35..0425bebd0f 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -31,6 +31,7 @@ config CPU_SPECIFIC_OPTIONS
 	select ARCH_VERSTAGE_X86_32
 	select ARCH_ROMSTAGE_X86_32
 	select ARCH_RAMSTAGE_X86_32
+	select GENERIC_GPIO_LIB
 	select IOAPIC
 	select HAVE_USBDEBUG_OPTIONS
 	select HAVE_HARD_RESET
diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c
index d49637a09c..7e19d996ff 100644
--- a/src/soc/amd/stoneyridge/gpio.c
+++ b/src/soc/amd/stoneyridge/gpio.c
@@ -16,8 +16,11 @@
  */
 
 #include <arch/io.h>
+#include <gpio.h>
 #include <soc/gpio.h>
 
+/* The following functions must be implemented by SoC/board code. */
+
 int gpio_get(gpio_t gpio_num)
 {
 	uint32_t reg;
@@ -26,3 +29,52 @@ int gpio_get(gpio_t gpio_num)
 
 	return !!(reg & GPIO_PIN_STS);
 }
+
+
+void gpio_set(gpio_t gpio_num, int value)
+{
+	uint32_t reg;
+
+	reg = read32((void *)(uintptr_t)gpio_num);
+	reg &= ~GPIO_OUTPUT_MASK;
+	reg |=  !!value << GPIO_OUTPUT_SHIFT;
+	write32((void *)(uintptr_t)gpio_num, reg);
+}
+
+void gpio_input_pulldown(gpio_t gpio_num)
+{
+	uint32_t reg;
+
+	reg = read32((void *)(uintptr_t)gpio_num);
+	reg &= ~GPIO_PULLUP_ENABLE;
+	reg |=  GPIO_PULLDOWN_ENABLE;
+	write32((void *)(uintptr_t)gpio_num, reg);
+}
+
+void gpio_input_pullup(gpio_t gpio_num)
+{
+	uint32_t reg;
+
+	reg = read32((void *)(uintptr_t)gpio_num);
+	reg &= ~GPIO_PULLDOWN_ENABLE;
+	reg |=  GPIO_PULLUP_ENABLE;
+	write32((void *)(uintptr_t)gpio_num, reg);
+}
+
+void gpio_input(gpio_t gpio_num)
+{
+	uint32_t reg;
+
+	reg = read32((void *)(uintptr_t)gpio_num);
+	reg &= ~GPIO_OUTPUT_ENABLE;
+	write32((void *)(uintptr_t)gpio_num, reg);
+}
+
+void gpio_output(gpio_t gpio_num, int value)
+{
+	uint32_t reg;
+
+	reg = read32((void *)(uintptr_t)gpio_num);
+	reg |=  GPIO_OUTPUT_ENABLE;
+	write32((void *)(uintptr_t)gpio_num, reg);
+}
diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h
index f873e52152..c43dd2767a 100644
--- a/src/soc/amd/stoneyridge/include/soc/gpio.h
+++ b/src/soc/amd/stoneyridge/include/soc/gpio.h
@@ -22,7 +22,10 @@
 #define CROS_GPIO_DEVICE_NAME	"AmdKern"
 
 #define GPIO_PIN_STS		(1 << 16)
-#define GPIO_OUTPUT_VALUE	(1 << 22)
+#define GPIO_PULLUP_ENABLE	(1 << 20)
+#define GPIO_PULLDOWN_ENABLE	(1 << 21)
+#define GPIO_OUTPUT_SHIFT	22
+#define GPIO_OUTPUT_MASK	(1 << GPIO_OUTPUT_SHIFT)
 #define GPIO_OUTPUT_ENABLE	(1 << 23)
 
 /* GPIO_0 - GPIO_62 */
@@ -126,6 +129,4 @@
 
 typedef uint32_t gpio_t;
 
-int gpio_get(gpio_t gpio_num);
-
 #endif	/* _STONEYRIDGE_GPIO_H_ */