diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 1c8f321924..b38265fdd4 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -571,8 +571,13 @@ static void glk_fsp_silicon_init_params_cb(
 	 * FSP provides UPD interface to execute IPC command. In order to
 	 * improve boot performance, configure PmicPmcIpcCtrl for PMC to program
 	 * PMIC PCH_PWROK delay.
-	*/
+	 */
 	silconfig->PmicPmcIpcCtrl = cfg->PmicPmcIpcCtrl;
+
+	/*
+	 * Options to disable XHCI Link Compliance Mode.
+	 */
+	silconfig->DisableComplianceMode = cfg->DisableComplianceMode;
 #endif
 }
 
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index 202f2acf1e..b9c9dc58ac 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -162,6 +162,12 @@ struct soc_intel_apollolake_config {
 	 * (31:24) + Register_Offset (23:16) + OR Value (15:8) + AND Value (7:0)
 	 */
 	uint32_t PmicPmcIpcCtrl;
+
+	/* Options to disable XHCI Link Compliance Mode. Default is FALSE to not
+	 * disable Compliance Mode. Set TRUE to disable Compliance Mode.
+	 * 0:FALSE(Default), 1:True.
+	 */
+	uint8_t DisableComplianceMode;
 };
 
 typedef struct soc_intel_apollolake_config config_t;