diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c
index 16a8a53c75..cdb871b916 100644
--- a/src/soc/amd/cezanne/early_fch.c
+++ b/src/soc/amd/cezanne/early_fch.c
@@ -13,12 +13,12 @@
 
 #include "chip.h"
 
-/* This table is for the initial conversion of all SCL pins to input with no pull. */
+/* Table to switch SCL pins to outputs to initially reset the I2C peripherals */
 static const struct soc_i2c_scl_pin i2c_scl_pins[] = {
-	{ PAD_GPI(I2C0_SCL_PIN, PULL_NONE), GPIO_I2C0_SCL },
-	{ PAD_GPI(I2C1_SCL_PIN, PULL_NONE), GPIO_I2C1_SCL },
-	{ PAD_GPI(I2C2_SCL_PIN, PULL_NONE), GPIO_I2C2_SCL },
-	{ PAD_GPI(I2C3_SCL_PIN, PULL_NONE), GPIO_I2C3_SCL },
+	{ PAD_GPO(I2C0_SCL_PIN, HIGH), GPIO_I2C0_SCL },
+	{ PAD_GPO(I2C1_SCL_PIN, HIGH), GPIO_I2C1_SCL },
+	{ PAD_GPO(I2C2_SCL_PIN, HIGH), GPIO_I2C2_SCL },
+	{ PAD_GPO(I2C3_SCL_PIN, HIGH), GPIO_I2C3_SCL },
 };
 
 static void reset_i2c_peripherals(void)
diff --git a/src/soc/amd/picasso/early_fch.c b/src/soc/amd/picasso/early_fch.c
index 110718e2e1..048ce12819 100644
--- a/src/soc/amd/picasso/early_fch.c
+++ b/src/soc/amd/picasso/early_fch.c
@@ -15,10 +15,10 @@
 
 #include "chip.h"
 
-/* This table is for the initial conversion of all SCL pins to input with no pull. */
+/* Table to switch SCL pins to outputs to initially reset the I2C peripherals */
 static const struct soc_i2c_scl_pin i2c_scl_pins[] = {
-	{ PAD_GPI(I2C2_SCL_PIN, PULL_NONE), GPIO_I2C2_SCL },
-	{ PAD_GPI(I2C3_SCL_PIN, PULL_NONE), GPIO_I2C3_SCL },
+	{ PAD_GPO(I2C2_SCL_PIN, HIGH), GPIO_I2C2_SCL },
+	{ PAD_GPO(I2C3_SCL_PIN, HIGH), GPIO_I2C3_SCL },
 	/* I2C4 is a peripheral device only */
 };
 
diff --git a/src/soc/amd/stoneyridge/bootblock.c b/src/soc/amd/stoneyridge/bootblock.c
index fc4284f502..499ff633d4 100644
--- a/src/soc/amd/stoneyridge/bootblock.c
+++ b/src/soc/amd/stoneyridge/bootblock.c
@@ -28,12 +28,12 @@
 #error "Error: CONFIG_PI_AGESA_CAR_HEAP_BASE must be >= 1MB"
 #endif
 
-/* This table is for the initial conversion of all SCL pins to input with no pull. */
+/* Table to switch SCL pins to outputs to initially reset the I2C peripherals */
 static const struct soc_i2c_scl_pin i2c_scl_pins[] = {
-	{ PAD_GPI(I2C0_SCL_PIN, PULL_NONE), GPIO_I2C0_SCL },
-	{ PAD_GPI(I2C1_SCL_PIN, PULL_NONE), GPIO_I2C1_SCL },
-	{ PAD_GPI(I2C2_SCL_PIN, PULL_NONE), GPIO_I2C2_SCL },
-	{ PAD_GPI(I2C3_SCL_PIN, PULL_NONE), GPIO_I2C3_SCL },
+	{ PAD_GPO(I2C0_SCL_PIN, HIGH), GPIO_I2C0_SCL },
+	{ PAD_GPO(I2C1_SCL_PIN, HIGH), GPIO_I2C1_SCL },
+	{ PAD_GPO(I2C2_SCL_PIN, HIGH), GPIO_I2C2_SCL },
+	{ PAD_GPO(I2C3_SCL_PIN, HIGH), GPIO_I2C3_SCL },
 };
 
 /* Set the MMIO Configuration Base Address, Bus Range, and misc MTRRs. */