soc/amd/cezanne: Add eSPI support
Change-Id: I7ed24e76df3c0542b04c0f072c1eaacceea4b71f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49965 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -38,6 +38,7 @@ config SOC_SPECIFIC_OPTIONS
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select SOC_AMD_COMMON_BLOCK_PCI
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select SOC_AMD_COMMON_BLOCK_PCI
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select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
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select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
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select SOC_AMD_COMMON_BLOCK_PSP_GEN2
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select SOC_AMD_COMMON_BLOCK_PSP_GEN2
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select SOC_AMD_COMMON_BLOCK_HAS_ESPI
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select SOC_AMD_COMMON_BLOCK_SMBUS
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select SOC_AMD_COMMON_BLOCK_SMBUS
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select SOC_AMD_COMMON_BLOCK_SMI
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select SOC_AMD_COMMON_BLOCK_SMI
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select SOC_AMD_COMMON_BLOCK_SMM
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select SOC_AMD_COMMON_BLOCK_SMM
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@ -1,6 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <amdblocks/acpimmio.h>
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#include <amdblocks/acpimmio.h>
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#include <amdblocks/espi.h>
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#include <amdblocks/lpc.h>
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#include <amdblocks/lpc.h>
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#include <amdblocks/smbus.h>
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#include <amdblocks/smbus.h>
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#include <console/console.h>
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#include <console/console.h>
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@ -32,4 +33,9 @@ void fch_pre_init(void)
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void fch_early_init(void)
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void fch_early_init(void)
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{
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{
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fch_print_pmxc0_status();
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fch_print_pmxc0_status();
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if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) {
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espi_setup();
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espi_configure_decodes();
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}
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}
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}
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